From a4737cc9305cbab9bb9c044fad48d75dff37568c Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Wed, 18 Nov 2015 18:55:59 -0500 Subject: Move core_selector config script to core/platform/common, generate project-specific core_selectors in the build directories. --- config/core_selector.v | 278 ------------------------------------------------- 1 file changed, 278 deletions(-) delete mode 100644 config/core_selector.v (limited to 'config/core_selector.v') diff --git a/config/core_selector.v b/config/core_selector.v deleted file mode 100644 index 298c39e..0000000 --- a/config/core_selector.v +++ /dev/null @@ -1,278 +0,0 @@ -// NOTE: This file is generated; do not edit by hand. - -module core_selector - ( - input wire sys_clk, - input wire sys_rst_n, - - input wire [16: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31: 0] sys_read_data, - input wire [31: 0] sys_write_data, - output wire sys_error, - - input wire noise, - output wire [7 : 0] debug - ); - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 9 bits specify core being addressed - wire [ 8: 0] addr_core_num = sys_eim_addr[16: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_BOARD_REGS = 9'h00; - localparam CORE_ADDR_COMM_REGS = 9'h01; - localparam CORE_ADDR_SHA256 = 9'h02; - localparam CORE_ADDR_AES = 9'h03; - localparam CORE_ADDR_TRNG = 9'h04; - localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h05; - localparam CORE_ADDR_ROSC_ENTROPY = 9'h06; - localparam CORE_ADDR_TRNG_MIXER = 9'h07; - localparam CORE_ADDR_TRNG_CSPRNG = 9'h08; - localparam CORE_ADDR_MODEXPS6 = 9'h14; - - - //---------------------------------------------------------------- - // BOARD_REGS - //---------------------------------------------------------------- - wire enable_board_regs = (addr_core_num == CORE_ADDR_BOARD_REGS); - wire [31: 0] read_data_board_regs; - wire error_board_regs; - - board_regs board_regs_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_board_regs & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_board_regs), - .error(error_board_regs) - ); - - reg [31: 0] read_data_board_regs_reg; - always @(posedge sys_clk) - read_data_board_regs_reg <= read_data_board_regs; - - - //---------------------------------------------------------------- - // COMM_REGS - //---------------------------------------------------------------- - wire enable_comm_regs = (addr_core_num == CORE_ADDR_COMM_REGS); - wire [31: 0] read_data_comm_regs; - wire error_comm_regs; - - comm_regs comm_regs_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_comm_regs & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_comm_regs), - .error(error_comm_regs) - ); - - reg [31: 0] read_data_comm_regs_reg; - always @(posedge sys_clk) - read_data_comm_regs_reg <= read_data_comm_regs; - - - //---------------------------------------------------------------- - // SHA256 - //---------------------------------------------------------------- - wire enable_sha256 = (addr_core_num == CORE_ADDR_SHA256); - wire [31: 0] read_data_sha256; - wire error_sha256; - - sha256 sha256_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha256), - .error(error_sha256) - ); - - reg [31: 0] read_data_sha256_reg; - always @(posedge sys_clk) - read_data_sha256_reg <= read_data_sha256; - - - //---------------------------------------------------------------- - // AES - //---------------------------------------------------------------- - wire enable_aes = (addr_core_num == CORE_ADDR_AES); - wire [31: 0] read_data_aes; - wire error_aes; - - aes aes_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_aes & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_aes), - .error(error_aes) - ); - - reg [31: 0] read_data_aes_reg; - always @(posedge sys_clk) - read_data_aes_reg <= read_data_aes; - - - //---------------------------------------------------------------- - // TRNG - //---------------------------------------------------------------- - wire enable_trng = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG + 9'h0f); - wire [31: 0] read_data_trng; - wire error_trng; - wire [3:0] trng_prefix = addr_core_num[3:0] - CORE_ADDR_TRNG; - - trng trng_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_trng & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address({trng_prefix, addr_core_reg}), - .write_data(sys_write_data), - .read_data(read_data_trng), - .error(error_trng), - - .avalanche_noise(noise), - .debug(debug) - ); - - reg [31: 0] read_data_trng_reg; - always @(posedge sys_clk) - read_data_trng_reg <= read_data_trng; - - - //---------------------------------------------------------------- - // MODEXPS6 - //---------------------------------------------------------------- - wire enable_modexps6 = (addr_core_num >= CORE_ADDR_MODEXPS6) && (addr_core_num <= CORE_ADDR_MODEXPS6 + 9'h03); - wire [31: 0] read_data_modexps6; - wire [1:0] modexps6_prefix = addr_core_num[1:0] - CORE_ADDR_MODEXPS6; - - modexps6_wrapper modexps6_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_modexps6 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address({modexps6_prefix, addr_core_reg}), - .write_data(sys_write_data), - .read_data(read_data_modexps6) - ); - - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexer - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - - case (addr_core_num) - CORE_ADDR_BOARD_REGS: - begin - sys_read_data_mux = read_data_board_regs_reg; - sys_error_mux = error_board_regs; - end - CORE_ADDR_COMM_REGS: - begin - sys_read_data_mux = read_data_comm_regs_reg; - sys_error_mux = error_comm_regs; - end - CORE_ADDR_SHA256: - begin - sys_read_data_mux = read_data_sha256_reg; - sys_error_mux = error_sha256; - end - CORE_ADDR_AES: - begin - sys_read_data_mux = read_data_aes_reg; - sys_error_mux = error_aes; - end - CORE_ADDR_TRNG: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_AVALANCHE_ENTROPY: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_ROSC_ENTROPY: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_TRNG_MIXER: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_TRNG_CSPRNG: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_MODEXPS6 + 0, - CORE_ADDR_MODEXPS6 + 1, - CORE_ADDR_MODEXPS6 + 2, - CORE_ADDR_MODEXPS6 + 3: - begin - sys_read_data_mux = read_data_modexps6; - sys_error_mux = 0; - end - - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - endcase - - -endmodule - - -//====================================================================== -// EOF core_selector.v -//====================================================================== -- cgit v1.2.3