From 0ef997a7567156ed271f36b64e077bd75c9e1798 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sun, 27 Sep 2015 18:58:10 -0400 Subject: Wedge modexps6 into the addressing scheme. Adjust timing of other cores. Tweak TRNG templates to support multiple instances, more for consistency than than because we really expect multiple TRNGs. --- config/config.py | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 5 deletions(-) (limited to 'config/config.py') diff --git a/config/config.py b/config/config.py index 4648f9d..bf77a36 100755 --- a/config/config.py +++ b/config/config.py @@ -35,6 +35,11 @@ Generate core_selector.v for a set of cores. # still takes up more than one new core slot even if trng uses the old # scheme internally. How many slots should we allocate, and what # addressing scheme is the trng core expecting to see? +# +# So perhaps a better plan would be to keep Paul's scheme and just +# give modexps6 four core's worth of space, passing a 10 bit composite +# address constructed in much the same way as the trng template +# already does. # Unrelated: Timing delays. Paul added extra registers to slow cores # other than modexps6 down by one clock cycle, to compensate for the @@ -200,6 +205,10 @@ class TRNGCore(InvertedResetCore): n = subcore.assign_core_number(n) return n + @property + def last_subcore_upper_instance_name(self): + return self.subcores[-1].upper_instance_name + def createInstance(self): return createInstance_template_TRNG.format(core = self) @@ -209,6 +218,20 @@ class TRNGCore(InvertedResetCore): def createMux(self): return super(TRNGCore, self).createMux() + "".join(subcore.createMux() for subcore in self.subcores) + +class ModExpS6Core(Core): + + def assign_core_number(self, n): + n = super(ModExpS6Core, self).assign_core_number(n) + return n + 3 + + def createInstance(self): + return createInstance_template_ModExpS6.format(core = self) + + def createMux(self): + return createMux_modexps6_template.format(core = self) + + # Hook special classes in as handlers for the cores that require them. Core.special_class.update( @@ -218,7 +241,8 @@ Core.special_class.update( sha1 = InvertedResetCore, sha256 = InvertedResetCore, sha512 = InvertedResetCore, - modexp = InvertedResetCore) + modexp = InvertedResetCore, + modexps6 = ModExpS6Core) # Templates (format strings), here instead of inline in the functions @@ -255,6 +279,38 @@ createInstance_template_generic = """\ .read_data(read_data_{core.instance_name}) ); + reg [31: 0] read_data_{core.instance_name}_reg; + always @(posedge sys_clk) + read_data_{core.instance_name}_reg <= read_data_{core.instance_name}; + + +""" + +# Template used by ModExpS6Core.createInstance(). This is different +# enough from the base template that it's easier to make this separate. + +createInstance_template_ModExpS6 = """\ + //---------------------------------------------------------------- + // {core.upper_instance_name} + //---------------------------------------------------------------- + wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 3); + wire [31: 0] read_data_{core.instance_name}; + wire error_{core.instance_name}; + wire [1:0] {core.instance_name}_prefix = addr_core_num[1:0] - CORE_ADDR_{core.upper_instance_name}; + + {core.name} {core.instance_name}_inst + ( + .clk(sys_clk), + {core.reset_pin}, + + .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address({{{core.instance_name}_prefix, addr_core_reg}}), + .write_data(sys_write_data), + .read_data(read_data_{core.instance_name}) + ); + """ @@ -266,10 +322,10 @@ createInstance_template_TRNG = """\ //---------------------------------------------------------------- // {core.upper_instance_name} //---------------------------------------------------------------- - wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG_CSPRNG); + wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.last_subcore_upper_instance_name}); wire [31: 0] read_data_{core.instance_name}; wire error_{core.instance_name}; - wire [3:0] trng_prefix = addr_core_num[3:0] - CORE_ADDR_TRNG; + wire [3:0] {core.instance_name}_prefix = addr_core_num[3:0] - CORE_ADDR_{core.upper_instance_name}; {core.name} {core.instance_name}_inst ( @@ -279,7 +335,7 @@ createInstance_template_TRNG = """\ .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), - .address({{trng_prefix, addr_core_reg}}), + .address({{{core.instance_name}_prefix, addr_core_reg}}), .write_data(sys_write_data), .read_data(read_data_{core.instance_name}), @@ -287,6 +343,10 @@ createInstance_template_TRNG = """\ .debug(debug) ); + reg [31: 0] read_data_{core.instance_name}_reg; + always @(posedge sys_clk) + read_data_{core.instance_name}_reg <= read_data_{core.instance_name}; + """ @@ -295,11 +355,25 @@ createInstance_template_TRNG = """\ createMux_template = """\ CORE_ADDR_{core.upper_instance_name}: begin - sys_read_data_mux = read_data_{core0.instance_name}; + sys_read_data_mux = read_data_{core0.instance_name}_reg; sys_error_mux = error_{core0.instance_name}; end """ +# Template for ModExpS6.createMux() method. + +createMux_modexps6_template = """\ + CORE_ADDR_{core.upper_instance_name} + 0, + CORE_ADDR_{core.upper_instance_name} + 1, + CORE_ADDR_{core.upper_instance_name} + 2, + CORE_ADDR_{core.upper_instance_name} + 3: + begin + sys_read_data_mux = read_data_{core.instance_name}; + sys_error_mux = error_{core.instance_name}; + end +""" + + # Top-level (createModule) template. createModule_template = """\ -- cgit v1.2.3