From 6a7b3fe6d5e83fc2ee236aae0799f74c92278685 Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Wed, 29 Apr 2015 13:19:15 -0400
Subject: Cleanup: add error port.

---
 common/rtl/novena_regs.v | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

(limited to 'common/rtl')

diff --git a/common/rtl/novena_regs.v b/common/rtl/novena_regs.v
index 716f650..eb89092 100644
--- a/common/rtl/novena_regs.v
+++ b/common/rtl/novena_regs.v
@@ -40,15 +40,19 @@
 
 module board_regs
   (
+   // Clock and reset.
    input wire           clk,
    input wire           rst,
 
+   // Control.
    input wire           cs,
    input wire           we,
 
-   input wire [ 7 : 0]  address,
+   // Data ports.
+   input wire [7 : 0]   address,
    input wire [31 : 0]  write_data,
-   output wire [31 : 0] read_data
+   output wire [31 : 0] read_data,
+   output wire          error
    );
 
 
@@ -70,6 +74,8 @@ module board_regs
    // Registers.
    //----------------------------------------------------------------
    reg [31: 0]          tmp_read_data;
+   reg                  write_error;
+   reg                  read_error;
 
    // dummy register to check that you can actually write something
    reg [31: 0]          reg_dummy;
@@ -85,6 +91,7 @@ module board_regs
    // Concurrent connectivity for ports etc.
    //----------------------------------------------------------------
    assign read_data = tmp_read_data;
+   assign error     = write_error | read_error;
    
    //----------------------------------------------------------------
    // storage registers for mapping memory to core interface
@@ -97,10 +104,14 @@ module board_regs
           end
         else if (cs && we)
           begin
+             write_error <= 0;
+
              // write operations
              case (address)
                ADDR_DUMMY_REG:
                  reg_dummy <= write_data;
+               default:
+                 write_error <= 1;
              endcase
           end
      end
@@ -108,6 +119,7 @@ module board_regs
    always @*
      begin
         tmp_read_data = 32'h00000000;
+        read_error    = 0;
 
         if (cs && !we)
           begin
@@ -121,6 +133,8 @@ module board_regs
                  tmp_read_data = core_version;
                ADDR_DUMMY_REG:
                  tmp_read_data = reg_dummy;
+               default:
+                 read_error = 1;
              endcase
           end
      end
-- 
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