From 2b374d2b124d073e37708843cf599256b2cd9aa1 Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Thu, 12 Nov 2015 16:48:01 -0500
Subject: Change reset to active-low.

---
 common/rtl/novena_regs.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'common/rtl/novena_regs.v')

diff --git a/common/rtl/novena_regs.v b/common/rtl/novena_regs.v
index eb89092..4edf028 100644
--- a/common/rtl/novena_regs.v
+++ b/common/rtl/novena_regs.v
@@ -42,7 +42,7 @@ module board_regs
   (
    // Clock and reset.
    input wire           clk,
-   input wire           rst,
+   input wire           reset_n,
 
    // Control.
    input wire           cs,
@@ -96,9 +96,9 @@ module board_regs
    //----------------------------------------------------------------
    // storage registers for mapping memory to core interface
    //----------------------------------------------------------------
-   always @ (posedge clk or posedge rst)
+   always @ (posedge clk or negedge reset_n)
      begin
-        if (rst)
+        if (!reset_n)
           begin
              reg_dummy <= {32{1'b0}};
           end
-- 
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