From 3d96445bf19f3fd15b2ad9fe4cd7a08bad9c0e41 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Mon, 19 Oct 2015 17:55:04 -0400 Subject: integrate Pavel's new clkmgr code --- .../ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v | 145 -------------------- .../clkmgr_dcm/simulation/functional/simcmds.tcl | 8 -- .../simulation/functional/simulate_isim.bat | 59 -------- .../simulation/functional/simulate_isim.sh | 61 --------- .../simulation/functional/simulate_mti.bat | 61 --------- .../simulation/functional/simulate_mti.do | 65 --------- .../simulation/functional/simulate_mti.sh | 61 --------- .../simulation/functional/simulate_ncsim.sh | 62 --------- .../simulation/functional/simulate_vcs.sh | 72 ---------- .../simulation/functional/ucli_commands.key | 5 - .../simulation/functional/vcs_session.tcl | 18 --- .../clkmgr_dcm/simulation/functional/wave.do | 60 --------- .../clkmgr_dcm/simulation/functional/wave.sv | 118 ---------------- .../clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v | 149 --------------------- .../clkmgr_dcm/simulation/timing/sdf_cmd_file | 2 - .../clkmgr_dcm/simulation/timing/simcmds.tcl | 9 -- .../clkmgr_dcm/simulation/timing/simulate_isim.sh | 62 --------- .../clkmgr_dcm/simulation/timing/simulate_mti.bat | 59 -------- .../clkmgr_dcm/simulation/timing/simulate_mti.do | 65 --------- .../clkmgr_dcm/simulation/timing/simulate_mti.sh | 61 --------- .../clkmgr_dcm/simulation/timing/simulate_ncsim.sh | 64 --------- .../clkmgr_dcm/simulation/timing/simulate_vcs.sh | 72 ---------- .../clkmgr_dcm/simulation/timing/ucli_commands.key | 5 - .../clkmgr_dcm/simulation/timing/vcs_session.tcl | 1 - .../ipcore/clkmgr_dcm/simulation/timing/wave.do | 71 ---------- 25 files changed, 1415 deletions(-) delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl delete mode 100644 common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do (limited to 'common/rtl/ipcore/clkmgr_dcm/simulation') diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v deleted file mode 100644 index ee24750..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v +++ /dev/null @@ -1,145 +0,0 @@ -// file: clkmgr_dcm_tb.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// - -//---------------------------------------------------------------------------- -// Clocking wizard demonstration testbench -//---------------------------------------------------------------------------- -// This demonstration testbench instantiates the example design for the -// clocking wizard. Input clocks are toggled, which cause the clocking -// network to lock and the counters to increment. -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -`define wait_lock @(posedge CLK_VALID) - -module clkmgr_dcm_tb (); - - // Clock to Q delay of 100ps - localparam TCQ = 100; - - - // timescale is 1ps/1ps - localparam ONE_NS = 1000; - localparam PHASE_ERR_MARGIN = 100; // 100ps - // how many cycles to run - localparam COUNT_PHASE = 1024; - // we'll be using the period in many locations - localparam time PER1 = 20.0*ONE_NS; - localparam time PER1_1 = PER1/2; - localparam time PER1_2 = PER1 - PER1/2; - - // Declare the input clock signals - reg CLK_IN1 = 1; - - // The high bit of the sampling counter - wire COUNT; - // Status and control signals - reg RESET = 0; - wire INPUT_CLK_STOPPED; - wire CLK_VALID; - reg COUNTER_RESET = 0; -wire [1:1] CLK_OUT; -//Freq Check using the M & D values setting and actual Frequency generated - - - // Input clock generation - //------------------------------------ - always begin - CLK_IN1 = #PER1_1 ~CLK_IN1; - CLK_IN1 = #PER1_2 ~CLK_IN1; - end - - // Test sequence - reg [15*8-1:0] test_phase = ""; - initial begin - // Set up any display statements using time to be readable - $timeformat(-12, 2, "ps", 10); - COUNTER_RESET = 0; - test_phase = "reset"; - RESET = 1; - #(PER1*6); - RESET = 0; - test_phase = "wait lock"; - `wait_lock; - #(PER1*6); - COUNTER_RESET = 1; - #(PER1*20) - COUNTER_RESET = 0; - - test_phase = "counting"; - #(PER1*COUNT_PHASE); - - $display("SIMULATION PASSED"); - $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); - $finish; - end - - // Instantiation of the example design containing the clock - // network and sampling counters - //--------------------------------------------------------- - clkmgr_dcm_exdes - #( - .TCQ (TCQ) - ) dut - (// Clock in ports - .CLK_IN1 (CLK_IN1), - // Reset for logic in example design - .COUNTER_RESET (COUNTER_RESET), - .CLK_OUT (CLK_OUT), - // High bits of the counters - .COUNT (COUNT), - // Status and control signals - .RESET (RESET), - .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED), - .CLK_VALID (CLK_VALID)); - -// Freq Check - -endmodule diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl deleted file mode 100644 index e19ead8..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl +++ /dev/null @@ -1,8 +0,0 @@ -# file: simcmds.tcl - -# create the simulation script -vcd dumpfile isim.vcd -vcd dumpvars -m /clkmgr_dcm_tb -l 0 -wave add / -run 50000ns -quit diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat deleted file mode 100644 index 80904cb..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_isim.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM - -vlogcomp -work work %XILINX%\verilog\src\glbl.v -vlogcomp -work work ..\..\..\clkmgr_dcm.v -vlogcomp -work work ..\..\example_design\clkmgr_dcm_exdes.v -vlogcomp -work work ..\clkmgr_dcm_tb.v - -REM compile the project -fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe - -REM run the simulation script -.\clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh deleted file mode 100644 index 9fb5029..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh +++ /dev/null @@ -1,61 +0,0 @@ -# file: simulate_isim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# nt -# create the project -vlogcomp -work work ${XILINX}/verilog/src/glbl.v -vlogcomp -work work ../../../clkmgr_dcm.v -vlogcomp -work work ../../example_design/clkmgr_dcm_exdes.v -vlogcomp -work work ../clkmgr_dcm_tb.v - -# compile the project -fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe - -# run the simulation script -./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat deleted file mode 100644 index 7497cd9..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat +++ /dev/null @@ -1,61 +0,0 @@ -REM file: simulate_mti.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM - -REM set up the working directory -vlib work - -REM compile all of the files -vlog -work work %XILINX%\verilog\src\glbl.v -vlog -work work ..\..\..\clkmgr_dcm.v -vlog -work work ..\..\example_design\clkmgr_dcm_exdes.v -vlog -work work ..\clkmgr_dcm_tb.v - -REM run the simulation -vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl - diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do deleted file mode 100644 index b0e526f..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $env(XILINX)/verilog/src/glbl.v -vlog -work work ../../../clkmgr_dcm.v -vlog -work work ../../example_design/clkmgr_dcm_exdes.v -vlog -work work ../clkmgr_dcm_tb.v - -# run the simulation -vsim -t ps -voptargs="+acc" -L unisims_ver work.clkmgr_dcm_tb work.glbl -do wave.do -log clkmgr_dcm_tb/dut/counter -log -r /* -run 50000ns diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh deleted file mode 100644 index 66099e0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh -# file: simulate_mti.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $XILINX/verilog/src/glbl.v -vlog -work work ../../../clkmgr_dcm.v -vlog -work work ../../example_design/clkmgr_dcm_exdes.v -vlog -work work ../clkmgr_dcm_tb.v - -# run the simulation -vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh deleted file mode 100644 index 01b0412..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh +++ /dev/null @@ -1,62 +0,0 @@ -#/bin/sh -# file: simulate_ncsim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -mkdir work - -# compile all of the files -ncvlog -work work ${XILINX}/verilog/src/glbl.v -ncvlog -work work ../../../clkmgr_dcm.v -ncvlog -work work ../../example_design/clkmgr_dcm_exdes.v -ncvlog -work work ../clkmgr_dcm_tb.v - -# elaborate and run the simulation -ncelab -work work -access +wc work.clkmgr_dcm_tb work.glbl -ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.clkmgr_dcm_tb diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh deleted file mode 100644 index 39668df..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh -# file: simulate_vcs.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# remove old files -rm -rf simv* csrc DVEfiles AN.DB - -# compile all of the files -# Note that -sverilog is not strictly required- You can -# remove the -sverilog if you change the type of the -# localparam for the periods in the testbench file to -# [63:0] from time -vlogan -sverilog \ - ${XILINX}/verilog/src/glbl.v \ - ../../../clkmgr_dcm.v \ - ../../example_design/clkmgr_dcm_exdes.v \ - ../clkmgr_dcm_tb.v - -# prepare the simulation -vcs +vcs+lic+wait -debug clkmgr_dcm_tb glbl - -# run the simulation -./simv -ucli -i ucli_commands.key - -# launch the viewer -dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key deleted file mode 100644 index 2bbdd0f..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ -call {$vcdpluson} -call {$vcdplusmemon(clkmgr_dcm_tb.dut.counter)} -run -call {$vcdplusclose} -quit diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl deleted file mode 100644 index 628e55a..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,18 +0,0 @@ -gui_open_window Wave -gui_sg_create clkmgr_dcm_group -gui_list_add_group -id Wave.1 {clkmgr_dcm_group} -gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.test_phase} -gui_set_radix -radix {ascii} -signals {clkmgr_dcm_tb.test_phase} -gui_sg_addsignal -group clkmgr_dcm_group {{Input_clocks}} -divider -gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.CLK_IN1} -gui_sg_addsignal -group clkmgr_dcm_group {{Output_clocks}} -divider -gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.clk} -gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.clk -gui_sg_addsignal -group clkmgr_dcm_group {{Status_control}} -divider -gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.RESET} -gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.USE_INCLK_STOPPED} -gui_sg_addsignal -group clkmgr_dcm_group {{Counters}} -divider -gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.COUNT} -gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.counter} -gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.counter -gui_zoom -window Wave.1 -full diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do deleted file mode 100644 index eee7422..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do +++ /dev/null @@ -1,60 +0,0 @@ -# file: wave.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -add wave -noupdate -format Literal -radix ascii /clkmgr_dcm_tb/test_phase -add wave -noupdate -divider {Input clocks} -add wave -noupdate -format Logic /clkmgr_dcm_tb/CLK_IN1 -add wave -noupdate -divider {Output clocks} -add wave -noupdate -format Logic /clkmgr_dcm_tb/dut/clk -add wave -noupdate -divider Status/control -add wave -noupdate -format Logic /clkmgr_dcm_tb/RESET -add wave -noupdate -format Logic /clkmgr_dcm_tb/INPUT_CLK_STOPPED -add wave -noupdate -divider Counters -add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/COUNT -add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/dut/counter diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv deleted file mode 100644 index c3c3eef..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv +++ /dev/null @@ -1,118 +0,0 @@ -# file: wave.sv -# -# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# Get the windows set up -# -if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { - window geometry "Design Browser 1" 1054x819+536+322 -} -window target "Design Browser 1" on -browser using {Design Browser 1} -browser set \ - -scope nc::clkmgr_dcm_tb -browser yview see nc::clkmgr_dcm_tb -browser timecontrol set -lock 0 - -if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { - window geometry "Waveform 1" 1010x600+0+541 -} -window target "Waveform 1" on -waveform using {Waveform 1} -waveform sidebar visibility partial -waveform set \ - -primarycursor TimeA \ - -signalnames name \ - -signalwidth 175 \ - -units ns \ - -valuewidth 75 -cursor set -using TimeA -time 0 -waveform baseline set -time 0 -waveform xview limits 0 20000n - -# -# Define signal groups -# -catch {group new -name {Output clocks} -overlay 0} -catch {group new -name {Status/control} -overlay 0} -catch {group new -name {Counters} -overlay 0} - -set id [waveform add -signals [list {nc::clkmgr_dcm_tb.CLK_IN1}]] - -group using {Output clocks} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {clkmgr_dcm_tb.dut.clk} \ - -group using {Counters} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {clkmgr_dcm_tb.dut.counter} \ - -group using {Status/control} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {nc::clkmgr_dcm_tb.RESET} {nc::clkmgr_dcm_tb.INPUT_CLK_STOPPED} - -set id [waveform add -signals [list {nc::clkmgr_dcm_tb.COUNT} ]] - -set id [waveform add -signals [list {nc::clkmgr_dcm_tb.test_phase} ]] -waveform format $id -radix %a - -set groupId [waveform add -groups {{Input clocks}}] -set groupId [waveform add -groups {{Output clocks}}] -set groupId [waveform add -groups {{Status/control}}] -set groupId [waveform add -groups {{Counters}}] diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v deleted file mode 100644 index 9618253..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v +++ /dev/null @@ -1,149 +0,0 @@ -// file: clkmgr_dcm_tb.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// - -//---------------------------------------------------------------------------- -// Clocking wizard demonstration testbench -//---------------------------------------------------------------------------- -// This demonstration testbench instantiates the example design for the -// clocking wizard. Input clocks are toggled, which cause the clocking -// network to lock and the counters to increment. -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -`define wait_lock @(posedge CLK_VALID) - -module clkmgr_dcm_tb (); - - // Clock to Q delay of 100ps - localparam TCQ = 100; - - - // timescale is 1ps/1ps - localparam ONE_NS = 1000; - localparam PHASE_ERR_MARGIN = 100; // 100ps - // how many cycles to run - localparam COUNT_PHASE = 1024; - // we'll be using the period in many locations - localparam time PER1 = 20.0*ONE_NS; - localparam time PER1_1 = PER1/2; - localparam time PER1_2 = PER1 - PER1/2; - - // Declare the input clock signals - reg CLK_IN1 = 1; - - // The high bit of the sampling counter - wire COUNT; - // Status and control signals - reg RESET = 0; - wire INPUT_CLK_STOPPED; - wire CLK_VALID; - reg COUNTER_RESET = 0; -wire [1:1] CLK_OUT; -//Freq Check using the M & D values setting and actual Frequency generated - - reg [13:0] timeout_counter = 14'b00000000000000; - - // Input clock generation - //------------------------------------ - always begin - CLK_IN1 = #PER1_1 ~CLK_IN1; - CLK_IN1 = #PER1_2 ~CLK_IN1; - end - - // Test sequence - reg [15*8-1:0] test_phase = ""; - initial begin - // Set up any display statements using time to be readable - $timeformat(-12, 2, "ps", 10); - $display ("Timing checks are not valid"); - COUNTER_RESET = 0; - test_phase = "reset"; - RESET = 1; - #(PER1*6); - RESET = 0; - test_phase = "wait lock"; - `wait_lock; - #(PER1*6); - COUNTER_RESET = 1; - #(PER1*19.5) - COUNTER_RESET = 0; - #(PER1*1) - $display ("Timing checks are valid"); - test_phase = "counting"; - #(PER1*COUNT_PHASE); - - $display("SIMULATION PASSED"); - $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); - $finish; - end - - - - // Instantiation of the example design containing the clock - // network and sampling counters - //--------------------------------------------------------- - clkmgr_dcm_exdes - dut - (// Clock in ports - .CLK_IN1 (CLK_IN1), - // Reset for logic in example design - .COUNTER_RESET (COUNTER_RESET), - .CLK_OUT (CLK_OUT), - // High bits of the counters - .COUNT (COUNT), - // Status and control signals - .RESET (RESET), - .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED), - .CLK_VALID (CLK_VALID)); - - -// Freq Check - -endmodule diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file deleted file mode 100644 index d59e315..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file +++ /dev/null @@ -1,2 +0,0 @@ -COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", -SCOPE = clkmgr_dcm_tb.dut; diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl deleted file mode 100644 index 14523af..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl +++ /dev/null @@ -1,9 +0,0 @@ -# file: simcmds.tcl - -# create the simulation script -vcd dumpfile isim.vcd -vcd dumpvars -m /clkmgr_dcm_tb -l 0 -wave add / -run 50000ns -quit - diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh deleted file mode 100644 index 0152cb0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh +++ /dev/null @@ -1,62 +0,0 @@ -# file: simulate_isim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# create the project -vlogcomp -work work ${XILINX}/verilog/src/glbl.v -vlogcomp -work work ../../implement/results/routed.v -vlogcomp -work work clkmgr_dcm_tb.v - -# compile the project -fuse work.clkmgr_dcm_tb work.glbl -L secureip -L simprims_ver -o clkmgr_dcm_isim.exe - -# run the simulation script -./clkmgr_dcm_isim.exe -tclbatch simcmds.tcl -sdfmax /clkmgr_dcm_tb/dut=../../implement/results/routed.sdf - -# run the simulation script -#./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat deleted file mode 100644 index 8a08dc0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_mti.bat -REM -REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -REM -REM This file contains confidential and proprietary information -REM of Xilinx, Inc. and is protected under U.S. and -REM international copyright and other intellectual property -REM laws. -REM -REM DISCLAIMER -REM This disclaimer is not a license and does not grant any -REM rights to the materials distributed herewith. Except as -REM otherwise provided in a valid license issued to you by -REM Xilinx, and to the maximum extent permitted by applicable -REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -REM (2) Xilinx shall not be liable (whether in contract or tort, -REM including negligence, or under any other theory of -REM liability) for any loss or damage of any kind or nature -REM related to, arising under or in connection with these -REM materials, including for any direct, or any indirect, -REM special, incidental, or consequential loss or damage -REM (including loss of data, profits, goodwill, or any type of -REM loss or damage suffered as a result of any action brought -REM by a third party) even if such damage or loss was -REM reasonably foreseeable or Xilinx had been advised of the -REM possibility of the same. -REM -REM CRITICAL APPLICATIONS -REM Xilinx products are not designed or intended to be fail- -REM safe, or for use in any application requiring fail-safe -REM performance, such as life-support or safety devices or -REM systems, Class III medical devices, nuclear facilities, -REM applications related to the deployment of airbags, or any -REM other applications that could lead to death, personal -REM injury, or severe property or environmental damage -REM (individually and collectively, "Critical -REM Applications"). Customer assumes the sole risk and -REM liability of any use of Xilinx products in Critical -REM Applications, subject only to applicable laws and -REM regulations governing limitations on product liability. -REM -REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -REM PART OF THIS FILE AT ALL TIMES. -REM -# set up the working directory -set work work -vlib work - -REM compile all of the files -vlog -work work %XILINX%\verilog\src\glbl.v -vlog -work work ..\..\implement\results\routed.v -vlog -work work clkmgr_dcm_tb.v - -REM run the simulation -vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do deleted file mode 100644 index bfeb9c5..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $env(XILINX)/verilog/src/glbl.v -vlog -work work ../../implement/results/routed.v -vlog -work work clkmgr_dcm_tb.v - -# run the simulation -vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl -#do wave.do -#log -r /* -run 50000ns - - diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh deleted file mode 100644 index b842adc..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh -# file: simulate_mti.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -set work work -vlib work - -# compile all of the files -vlog -work work $XILINX/verilog/src/glbl.v -vlog -work work ../../implement/results/routed.v -vlog -work work clkmgr_dcm_tb.v - -# run the simulation -vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh deleted file mode 100644 index fd18dde..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh -# file: simulate_ncsim.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# set up the working directory -mkdir work - -# compile all of the files -ncvlog -work work ${XILINX}/verilog/src/glbl.v -ncvlog -work work ../../implement/results/routed.v -ncvlog -work work clkmgr_dcm_tb.v - -# elaborate and run the simulation -ncsdfc ../../implement/results/routed.sdf - -ncelab -work work -access +wc -pulse_r 10 -nonotifier work.clkmgr_dcm_tb work.glbl -sdf_cmd_file sdf_cmd_file -ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.clkmgr_dcm_tb - diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh deleted file mode 100644 index 26a8c27..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh -# file: simulate_vcs.sh -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# remove old files -rm -rf simv* csrc DVEfiles AN.DB - -# compile all of the files -# Note that -sverilog is not strictly required- You can -# remove the -sverilog if you change the type of the -# localparam for the periods in the testbench file to -# [63:0] from time - vlogan -sverilog \ - clkmgr_dcm_tb.v \ - ../../implement/results/routed.v - - -# prepare the simulation -vcs -sdf max:clkmgr_dcm_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ - +libext+.v -debug clkmgr_dcm_tb.v ../../implement/results/routed.v - -# run the simulation -./simv -ucli -i ucli_commands.key - -# launch the viewer -#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key deleted file mode 100644 index b32669e..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ - -call {$vcdpluson} -run 50000ns -call {$vcdplusclose} -quit diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl deleted file mode 100644 index 6cc6e24..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl +++ /dev/null @@ -1 +0,0 @@ -gui_open_window Wave diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do deleted file mode 100644 index 7cc804b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do +++ /dev/null @@ -1,71 +0,0 @@ -# file: wave.do -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /clkmgr_dcm_tb/CLK_IN1 -add wave -noupdate /clkmgr_dcm_tb/COUNT -add wave -noupdate /clkmgr_dcm_tb/RESET -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} -configure wave -namecolwidth 238 -configure wave -valuecolwidth 107 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {74848022 ps} -- cgit v1.2.3