From 02ca34c86ba35a6036be316f7e31d0216e3a67e0 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Fri, 17 Jul 2015 13:26:46 -0400 Subject: remove all non-essential files related to clkmgr_dcm --- .../clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf | 60 -------- .../clkmgr_dcm/example_design/clkmgr_dcm_exdes.v | 164 --------------------- .../clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc | 69 --------- 3 files changed, 293 deletions(-) delete mode 100644 common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf delete mode 100644 common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v delete mode 100644 common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc (limited to 'common/rtl/ipcore/clkmgr_dcm/example_design') diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf deleted file mode 100644 index dffb528..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf +++ /dev/null @@ -1,60 +0,0 @@ -# file: clkmgr_dcm_exdes.ucf -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; - - -# FALSE PATH constraints -PIN "COUNTER_RESET" TIG; -PIN "RESET" TIG; - diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v deleted file mode 100644 index 10627b3..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v +++ /dev/null @@ -1,164 +0,0 @@ -// file: clkmgr_dcm_exdes.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// - -//---------------------------------------------------------------------------- -// Clocking wizard example design -//---------------------------------------------------------------------------- -// This example design instantiates the created clocking network, where each -// output clock drives a counter. The high bit of each counter is ported. -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -module clkmgr_dcm_exdes - #( - parameter TCQ = 100 - ) - (// Clock in ports - input CLK_IN1, - // Reset that only drives logic in example design - input COUNTER_RESET, - output [1:1] CLK_OUT, - // High bits of counters driven by clocks - output COUNT, - // Status and control signals - input RESET, - output INPUT_CLK_STOPPED, - output CLK_VALID - ); - - // Parameters for the counters - //------------------------------- - // Counter width - localparam C_W = 16; - // Create reset for the counters - wire reset_int = RESET || COUNTER_RESET; - - reg rst_sync; - reg rst_sync_int; - reg rst_sync_int1; - reg rst_sync_int2; - - - - // Declare the clocks and counter - wire clk_int; - wire clk_n; - wire clk; - reg [C_W-1:0] counter; - - // Insert BUFGs on all input clocks that don't already have them - //-------------------------------------------------------------- - BUFG clkin1_buf - (.O (clk_in1_buf), - .I (CLK_IN1)); - - // Instantiation of the clocking network - //-------------------------------------- - clkmgr_dcm clknetwork - (// Clock in ports - .CLK_IN1 (clk_in1_buf), - // Clock out ports - .CLK_OUT1 (clk_int), - // Status and control signals - .RESET (RESET), - .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED), - .CLK_VALID (CLK_VALID)); - - assign clk_n = ~clk; - - ODDR2 clkout_oddr - (.Q (CLK_OUT[1]), - .C0 (clk), - .C1 (clk_n), - .CE (1'b1), - .D0 (1'b1), - .D1 (1'b0), - .R (1'b0), - .S (1'b0)); - - // Connect the output clocks to the design - //----------------------------------------- - assign clk = clk_int; - - - // Reset synchronizer - //----------------------------------- - always @(posedge reset_int or posedge clk) begin - if (reset_int) begin - rst_sync <= 1'b1; - rst_sync_int <= 1'b1; - rst_sync_int1 <= 1'b1; - rst_sync_int2 <= 1'b1; - end - else begin - rst_sync <= 1'b0; - rst_sync_int <= rst_sync; - rst_sync_int1 <= rst_sync_int; - rst_sync_int2 <= rst_sync_int1; - end - end - - - // Output clock sampling - //----------------------------------- - always @(posedge clk or posedge rst_sync_int2) begin - if (rst_sync_int2) begin - counter <= #TCQ { C_W { 1'b 0 } }; - end else begin - counter <= #TCQ counter + 1'b 1; - end - end - - // alias the high bit to the output - assign COUNT = counter[C_W-1]; - - - -endmodule diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc deleted file mode 100644 index 787023d..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc +++ /dev/null @@ -1,69 +0,0 @@ -# file: clkmgr_dcm_exdes.xdc -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] -set_propagated_clock CLK_IN1 -set_input_jitter CLK_IN1 0.2 - -# FALSE PATH constraint added on COUNTER_RESET -set_false_path -from [get_ports "COUNTER_RESET"] -set_false_path -from [get_ports "RESET"] - -# Derived clock periods. These are commented out because they are -# automatically propogated by the tools -# However, if you'd like to use them for module level testing, you -# can copy them into your module level timing checks -#----------------------------------------------------------------- - -#----------------------------------------------------------------- - -#----------------------------------------------------------------- -- cgit v1.2.3