From 283bfbeeb7fb5767815c10ea98bb155638d4bfb3 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 17 Mar 2015 13:49:30 +0100 Subject: Rearrange cores. --- common/rtl/ipcore/clkmgr_dcm.veo | 79 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 common/rtl/ipcore/clkmgr_dcm.veo (limited to 'common/rtl/ipcore/clkmgr_dcm.veo') diff --git a/common/rtl/ipcore/clkmgr_dcm.veo b/common/rtl/ipcore/clkmgr_dcm.veo new file mode 100644 index 0000000..c4e1d31 --- /dev/null +++ b/common/rtl/ipcore/clkmgr_dcm.veo @@ -0,0 +1,79 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____50.000______0.000______50.0______200.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary______________50____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clkmgr_dcm instance_name + (// Clock in ports + .CLK_IN1(CLK_IN1), // IN + // Clock out ports + .CLK_OUT1(CLK_OUT1), // OUT + // Status and control signals + .RESET(RESET),// IN + .INPUT_CLK_STOPPED(INPUT_CLK_STOPPED), // OUT + .CLK_VALID(CLK_VALID)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- -- cgit v1.2.3