From 3d96445bf19f3fd15b2ad9fe4cd7a08bad9c0e41 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Mon, 19 Oct 2015 17:55:04 -0400 Subject: integrate Pavel's new clkmgr code --- common/rtl/ipcore/clkmgr_dcm.v | 148 ----------------------------------------- 1 file changed, 148 deletions(-) delete mode 100644 common/rtl/ipcore/clkmgr_dcm.v (limited to 'common/rtl/ipcore/clkmgr_dcm.v') diff --git a/common/rtl/ipcore/clkmgr_dcm.v b/common/rtl/ipcore/clkmgr_dcm.v deleted file mode 100644 index 71477a8..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.v +++ /dev/null @@ -1,148 +0,0 @@ -// file: clkmgr_dcm.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// "Output Output Phase Duty Pk-to-Pk Phase" -// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" -//---------------------------------------------------------------------------- -// CLK_OUT1____50.000______0.000______50.0______200.000____150.000 -// -//---------------------------------------------------------------------------- -// "Input Clock Freq (MHz) Input Jitter (UI)" -//---------------------------------------------------------------------------- -// __primary______________50____________0.010 - -`timescale 1ps/1ps - -(* CORE_GENERATION_INFO = "clkmgr_dcm,clk_wiz_v3_6,{component_name=clkmgr_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *) -module clkmgr_dcm - (// Clock in ports - input CLK_IN1, - // Clock out ports - output CLK_OUT1, - // Status and control signals - input RESET, - output INPUT_CLK_STOPPED, - output CLK_VALID - ); - - // Input buffering - //------------------------------------ - assign clkin1 = CLK_IN1; - - - // Clocking primitive - //------------------------------------ - - // Instantiation of the DCM primitive - // * Unused inputs are tied off - // * Unused outputs are labeled unused - wire psdone_unused; - wire locked_int; - wire [7:0] status_int; - wire clkfb; - wire clk0; - - DCM_SP - #(.CLKDV_DIVIDE (2.000), - .CLKFX_DIVIDE (1), - .CLKFX_MULTIPLY (4), - .CLKIN_DIVIDE_BY_2 ("FALSE"), - .CLKIN_PERIOD (20.0), - .CLKOUT_PHASE_SHIFT ("NONE"), - .CLK_FEEDBACK ("1X"), - .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), - .PHASE_SHIFT (0), - .STARTUP_WAIT ("FALSE")) - dcm_sp_inst - // Input clock - (.CLKIN (clkin1), - .CLKFB (clkfb), - // Output clocks - .CLK0 (clk0), - .CLK90 (), - .CLK180 (), - .CLK270 (), - .CLK2X (), - .CLK2X180 (), - .CLKFX (), - .CLKFX180 (), - .CLKDV (), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - // Other control and status signals - .LOCKED (locked_int), - .STATUS (status_int), - - .RST (RESET), - // Unused pin- tie low - .DSSEN (1'b0)); - - assign INPUT_CLK_STOPPED = status_int[1]; - assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[1] == 1'b 0 ) ); - - // Output buffering - //----------------------------------- - assign clkfb = CLK_OUT1; - - BUFG clkout1_buf - (.O (CLK_OUT1), - .I (clk0)); - - - - -endmodule -- cgit v1.2.3