From 2de0824f026172dafe9f83564c66df12d5f1da64 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 21 Apr 2015 12:36:44 -0400 Subject: Unify eim and i2c memory map, unify apps, build libraries. --- eim/sw/Makefile | 31 -- eim/sw/cryptech_memory_map.h | 217 ------------- eim/sw/hash_eim.c | 293 ------------------ eim/sw/hash_tester_eim.c | 683 ----------------------------------------- eim/sw/novena-eim.c | 708 ------------------------------------------- eim/sw/novena-eim.h | 52 ---- eim/sw/tc_eim.c | 185 ----------- eim/sw/tc_eim.h | 50 --- eim/sw/trng_extractor_eim.c | 161 ---------- eim/sw/trng_tester_eim.c | 371 ----------------------- i2c/sw/Makefile | 29 -- i2c/sw/cryptech_memory_map.h | 217 ------------- i2c/sw/hash_i2c.c | 288 ------------------ i2c/sw/hash_tester_i2c.c | 634 -------------------------------------- i2c/sw/tc_i2c.c | 331 -------------------- i2c/sw/tc_i2c.h | 55 ---- i2c/sw/trng_extractor_i2c.c | 169 ----------- i2c/sw/trng_tester_i2c.c | 321 -------------------- sw/Makefile | 44 +++ sw/Makefile.i2c | 44 +++ sw/cryptech.h | 231 ++++++++++++++ sw/hash.c | 291 ++++++++++++++++++ sw/hash_tester.c | 681 +++++++++++++++++++++++++++++++++++++++++ sw/novena-eim.c | 708 +++++++++++++++++++++++++++++++++++++++++++ sw/novena-eim.h | 52 ++++ sw/tc_eim.c | 208 +++++++++++++ sw/tc_i2c.c | 335 ++++++++++++++++++++ sw/trng_extractor.c | 158 ++++++++++ sw/trng_tester.c | 371 +++++++++++++++++++++++ 29 files changed, 3123 insertions(+), 4795 deletions(-) delete mode 100755 eim/sw/Makefile delete mode 100644 eim/sw/cryptech_memory_map.h delete mode 100644 eim/sw/hash_eim.c delete mode 100644 eim/sw/hash_tester_eim.c delete mode 100644 eim/sw/novena-eim.c delete mode 100644 eim/sw/novena-eim.h delete mode 100644 eim/sw/tc_eim.c delete mode 100644 eim/sw/tc_eim.h delete mode 100644 eim/sw/trng_extractor_eim.c delete mode 100644 eim/sw/trng_tester_eim.c delete mode 100755 i2c/sw/Makefile delete mode 100644 i2c/sw/cryptech_memory_map.h delete mode 100644 i2c/sw/hash_i2c.c delete mode 100644 i2c/sw/hash_tester_i2c.c delete mode 100644 i2c/sw/tc_i2c.c delete mode 100644 i2c/sw/tc_i2c.h delete mode 100644 i2c/sw/trng_extractor_i2c.c delete mode 100644 i2c/sw/trng_tester_i2c.c create mode 100755 sw/Makefile create mode 100755 sw/Makefile.i2c create mode 100644 sw/cryptech.h create mode 100644 sw/hash.c create mode 100644 sw/hash_tester.c create mode 100644 sw/novena-eim.c create mode 100644 sw/novena-eim.h create mode 100644 sw/tc_eim.c create mode 100644 sw/tc_i2c.c create mode 100644 sw/trng_extractor.c create mode 100644 sw/trng_tester.c diff --git a/eim/sw/Makefile b/eim/sw/Makefile deleted file mode 100755 index 8b5f974..0000000 --- a/eim/sw/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -all: hash_tester_eim trng_tester_eim hash_eim trng_extractor_eim - -.c.o: - gcc -c -Wall -o $@ $< - -hash_tester_eim: hash_tester_eim.o novena-eim.o tc_eim.o - gcc -o $@ $^ - -hash_tester_eim.o: hash_tester_eim.c tc_eim.h cryptech_memory_map.h - -trng_tester_eim: trng_tester_eim.o novena-eim.o tc_eim.o - gcc -o $@ $^ - -trng_tester_eim.o: trng_tester_eim.c tc_eim.h cryptech_memory_map.h - -hash_eim: hash_eim.o novena-eim.o tc_eim.o - gcc -o $@ $^ - -hash_eim.o: hash_eim.c tc_eim.h - -trng_extractor_eim: trng_extractor_eim.o novena-eim.o tc_eim.o - gcc -o $@ $^ - -trng_extractor_eim.o: trng_extractor_eim.c tc_eim.h cryptech_memory_map.h - -novena-eim.o: novena-eim.c novena-eim.h - -tc_eim.o: tc_eim.c tc_eim.h novena-eim.h - -clean: - rm -f *.o hash_tester_eim trng_tester_eim hash_eim trng_extractor_eim diff --git a/eim/sw/cryptech_memory_map.h b/eim/sw/cryptech_memory_map.h deleted file mode 100644 index 5cf7f42..0000000 --- a/eim/sw/cryptech_memory_map.h +++ /dev/null @@ -1,217 +0,0 @@ -//====================================================================== -// -// cryptech_memory_map.h -// --------------------- -// The memory map for Cryptech cores. -// -// -// Authors: Joachim Strombergson, Paul Selkirk -// Copyright (c) 2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -// BASE_ADDR, SEGMENT_SIZE, and ADDR are defined in tc_[eim|i2c].h, -// which #includes this file. - -// default definitions from i2c, because defaults are good -#ifndef BASE_ADDR -#define BASE_ADDR 0 -#endif -#ifndef SEGMENT_SIZE -#define SEGMENT_SIZE 0x2000 -#endif -#ifndef ADDR -#define ADDR(x) (x) -#endif - -#ifndef bitsToBytes -#define bitsToBytes(x) (x / 8) -#endif - -// Segments. -#define SEGMENT_OFFSET_GLOBALS BASE_ADDR + (0 * SEGMENT_SIZE) -#define SEGMENT_OFFSET_HASHES BASE_ADDR + (1 * SEGMENT_SIZE) -#define SEGMENT_OFFSET_RNGS BASE_ADDR + (2 * SEGMENT_SIZE) -#define SEGMENT_OFFSET_CIPHERS BASE_ADDR + (3 * SEGMENT_SIZE) - - -// addresses and codes common to all cores -#define ADDR_NAME0 ADDR(0x00) -#define ADDR_NAME1 ADDR(0x01) -#define ADDR_VERSION ADDR(0x02) - - -//------------------------------------------------------------------ -// Board segment. -// Board-level registers and communication channel registers -//------------------------------------------------------------------ -#define BOARD_CORE_SIZE ADDR(0x100) - -#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0 * BOARD_CORE_SIZE) -#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 -#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 -#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION -#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + ADDR(0xFF) - -#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (1 * BOARD_CORE_SIZE) -#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 -#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 -#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION - - -//------------------------------------------------------------------ -// Hashes segment. -//------------------------------------------------------------------ -#define HASH_CORE_SIZE ADDR(0x100) - -// addresses and codes common to all hash cores */ -#define ADDR_CTRL ADDR(0x8) -#define CTRL_INIT_CMD 1 -#define CTRL_NEXT_CMD 2 -#define ADDR_STATUS ADDR(0x9) -#define STATUS_READY_BIT 1 -#define STATUS_VALID_BIT 2 -#define ADDR_BLOCK ADDR(0x10) -#define ADDR_DIGEST ADDR(0x20) // except SHA512 - -// addresses and codes for the specific hash cores. -#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0 * HASH_CORE_SIZE) -#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 -#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 -#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION -#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL -#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS -#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK -#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST -#define SHA1_BLOCK_LEN bitsToBytes(512) -#define SHA1_LENGTH_LEN bitsToBytes(64) -#define SHA1_DIGEST_LEN bitsToBytes(160) - -#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1 * HASH_CORE_SIZE) -#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 -#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 -#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION -#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL -#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS -#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK -#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST -#define SHA256_BLOCK_LEN bitsToBytes(512) -#define SHA256_LENGTH_LEN bitsToBytes(64) -#define SHA256_DIGEST_LEN bitsToBytes(256) - -#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2 * HASH_CORE_SIZE) -#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 -#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 -#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION -#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL -#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS -#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK -#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + ADDR(0x40) -#define SHA512_BLOCK_LEN bitsToBytes(1024) -#define SHA512_LENGTH_LEN bitsToBytes(128) -#define SHA512_224_DIGEST_LEN bitsToBytes(224) -#define SHA512_256_DIGEST_LEN bitsToBytes(256) -#define SHA384_DIGEST_LEN bitsToBytes(384) -#define SHA512_DIGEST_LEN bitsToBytes(512) -#define MODE_SHA_512_224 0 << 2 -#define MODE_SHA_512_256 1 << 2 -#define MODE_SHA_384 2 << 2 -#define MODE_SHA_512 3 << 2 - - -// ----------------------------------------------------------------- -// TRNG segment. -// ----------------------------------------------------------------- -#define TRNG_CORE_SIZE ADDR(0x100) - -// addresses and codes for the TRNG cores */ -#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0 * TRNG_CORE_SIZE) -#define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 -#define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 -#define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION -#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + ADDR(0x10) -#define TRNG_CTRL_DISCARD 1 -#define TRNG_CTRL_TEST_MODE 2 -#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + ADDR(0x11) -// no status bits defined (yet) -#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + ADDR(0x13) - -#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (5 * TRNG_CORE_SIZE) -#define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 -#define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 -#define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION -#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + ADDR(0x10) -#define ENTROPY1_CTRL_ENABLE 1 -#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + ADDR(0x11) -#define ENTROPY1_STATUS_VALID 1 -#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + ADDR(0x20) -#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + ADDR(0x30) - -#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (6 * TRNG_CORE_SIZE) -#define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 -#define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 -#define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION -#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + ADDR(0x10) -#define ENTROPY2_CTRL_ENABLE 1 -#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + ADDR(0x11) -#define ENTROPY2_STATUS_VALID 1 -#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + ADDR(0x18) -#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + ADDR(0x19) -#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + ADDR(0x20) -#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + ADDR(0x21) -#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + ADDR(0x22) - -#define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * TRNG_CORE_SIZE) -#define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 -#define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 -#define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION -#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + ADDR(0x10) -#define MIXER_CTRL_ENABLE 1 -#define MIXER_CTRL_RESTART 2 -#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + ADDR(0x11) -// no status bits defined (yet) -#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + ADDR(0x20) - -#define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * TRNG_CORE_SIZE) -#define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 -#define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 -#define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION -#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + ADDR(0x10) -#define CSPRNG_CTRL_ENABLE 1 -#define CSPRNG_CTRL_SEED 2 -#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + ADDR(0x11) -#define CSPRNG_STATUS_VALID 1 -#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + ADDR(0x20) -#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + ADDR(0x40) -#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + ADDR(0x41) -#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + ADDR(0x42) - -//====================================================================== -// EOF cryptech_memory_map.h -//====================================================================== diff --git a/eim/sw/hash_eim.c b/eim/sw/hash_eim.c deleted file mode 100644 index e698129..0000000 --- a/eim/sw/hash_eim.c +++ /dev/null @@ -1,293 +0,0 @@ -/* - * hash.c - * ------ - * This program uses the coretest_hashes subsystem to produce a - * cryptographic hash of a file or input stream. It is a generalization - * of the hash_tester.c test program. - * - * Authors: Joachim Strömbergson, Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tc_eim.h" -#include "cryptech_memory_map.h" - -char *usage = -"Usage: %s [-d] [-v] [-q] [algorithm [file]]\n" -"algorithms: sha-1, sha-256, sha-512/224, sha-512/256, sha-384, sha-512\n"; - -int debug = 0; -int quiet = 0; -int verbose = 0; - - -/* ---------------- algorithm lookup code ---------------- */ - -struct ctrl { - char *name; - off_t block_addr; - int block_len; - off_t digest_addr; - int digest_len; - int mode; -} ctrl[] = { - { "sha-1", SHA1_ADDR_BLOCK, SHA1_BLOCK_LEN, - SHA1_ADDR_DIGEST, SHA1_DIGEST_LEN, 0 }, - { "sha-256", SHA256_ADDR_BLOCK, SHA256_BLOCK_LEN, - SHA256_ADDR_DIGEST, SHA256_DIGEST_LEN, 0 }, - { "sha-512/224", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA512_224_DIGEST_LEN, MODE_SHA_512_224 }, - { "sha-512/256", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA512_256_DIGEST_LEN, MODE_SHA_512_256 }, - { "sha-384", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA384_DIGEST_LEN, MODE_SHA_384 }, - { "sha-512", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA512_DIGEST_LEN, MODE_SHA_512 }, - { NULL, 0, 0, 0 } -}; - -/* return the control structure for the given algorithm */ -struct ctrl *find_algo(char *algo) -{ - int i; - - for (i = 0; ctrl[i].name != NULL; ++i) - if (strcmp(ctrl[i].name, algo) == 0) - return &ctrl[i]; - - fprintf(stderr, "algorithm \"%s\" not found\n\n", algo); - fprintf(stderr, usage, "hash"); - return NULL; -} - -/* ---------------- hash ---------------- */ - -static int transmit(off_t offset, uint8_t *block, int blen, int mode, int first) -{ - off_t base = offset & ~(0x1ff); - uint8_t ctrl_cmd[4] = { 0 }; - - if (tc_write(offset, block, blen) != 0) - return 1; - - ctrl_cmd[3] = (first ? CTRL_INIT_CMD : CTRL_NEXT_CMD) | mode; - - return - tc_write(base + ADDR_CTRL, ctrl_cmd, 4) || - tc_wait_ready(base + ADDR_STATUS); -} - -static int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen, - uint8_t mode, long long tlen, int first) -{ - assert(flen < blen); - - block[flen++] = 0x80; - memset(block + flen, 0, blen - flen); - - if (blen - flen < ((blen == 64) ? 8 : 16)) { - if (transmit(offset, block, blen, mode, first) != 0) - return 1; - first = 0; - memset(block, 0, blen); - } - - /* properly the length is 128 bits for sha-512, but we can't - * actually count above 64 bits - */ - ((uint32_t *)block)[blen/4 - 2] = htonl((tlen >> 32) & 0xffff); - ((uint32_t *)block)[blen/4 - 1] = htonl(tlen & 0xffff); - - return transmit(offset, block, blen, mode, first); -} - -/* return number of digest bytes read */ -static int hash(char *algo, char *file, uint8_t *digest) -{ - uint8_t block[SHA512_BLOCK_LEN]; - struct ctrl *ctrl; - int in_fd = 0; /* stdin */ - off_t baddr, daddr; - int blen, dlen, mode; - int nblk, nread, first; - int ret = -1; - struct timeval start, stop, difftime; - - ctrl = find_algo(algo); - if (ctrl == NULL) - return -1; - baddr = ctrl->block_addr; - blen = ctrl->block_len; - daddr = ctrl->digest_addr; - dlen = ctrl->digest_len; - mode = ctrl->mode; - - if (strcmp(file, "-") != 0) { - in_fd = open(file, O_RDONLY); - if (in_fd < 0) { - perror("open"); - return -1; - } - } - - if (verbose) { - if (gettimeofday(&start, NULL) < 0) { - perror("gettimeofday"); - goto out; - } - } - - for (nblk = 0, first = 1; ; ++nblk, first = 0) { - nread = read(in_fd, block, blen); - if (nread < 0) { - /* read error */ - perror("read"); - goto out; - } - else if (nread < blen) { - /* partial read = last block */ - if (pad_transmit(baddr, block, nread, blen, mode, - (nblk * blen + nread) * 8, first) != 0) - goto out; - break; - } - else { - /* full block read */ - if (transmit(baddr, block, blen, mode, first) != 0) - goto out; - } - } - - /* Strictly speaking we should query "valid" status before reading digest, - * but transmit() waits for "ready" status before returning, and the SHA - * cores always assert valid before ready. - */ - if (tc_read(daddr, digest, dlen) != 0) { - perror("i2c read failed"); - goto out; - } - - if (verbose) { - if (gettimeofday(&stop, NULL) < 0) { - perror("gettimeofday"); - goto out; - } - timersub(&stop, &start, &difftime); - printf("%d blocks written in %d.%03d sec (%.3f blocks/sec)\n", - nblk, (int)difftime.tv_sec, (int)difftime.tv_usec/1000, - (float)nblk / ((float)difftime.tv_sec + ((float)difftime.tv_usec)/1000000)); - } - - ret = dlen; -out: - if (in_fd != 0) - close(in_fd); - return ret; -} - -/* ---------------- main ---------------- */ - -int main(int argc, char *argv[]) -{ - int i, opt; - char *algo = "sha-1"; - char *file = "-"; - uint8_t digest[512/8]; - int dlen; - - while ((opt = getopt(argc, argv, "h?dvq")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'd': - debug = 1; - break; - case 'v': - verbose = 1; - break; - case 'q': - quiet = 1; - break; - default: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - - if (optind < argc) { - algo = argv[optind]; - ++optind; - } - else { - if (!quiet) - printf("defaulting to algorithm \"%s\"\n", algo); - } - - if (optind < argc) { - file = argv[optind]; - ++optind; - } - else { - if (!quiet) - printf("reading from stdin\n"); - } - - dlen = hash(algo, file, digest); - if (dlen < 0) - return EXIT_FAILURE; - - for (i = 0; i < dlen; ++i) { - printf("%02x", digest[i]); - if (i % 16 == 15) - printf("\n"); - else if (i % 4 == 3) - printf(" "); - } - if (dlen % 16 != 0) - printf("\n"); - - return EXIT_SUCCESS; -} diff --git a/eim/sw/hash_tester_eim.c b/eim/sw/hash_tester_eim.c deleted file mode 100644 index 8b4f04b..0000000 --- a/eim/sw/hash_tester_eim.c +++ /dev/null @@ -1,683 +0,0 @@ -/* - * hash_tester.c - * -------------- - * This program sends several commands to the coretest_hashes subsystem - * in order to verify the SHA-1, SHA-256 and SHA-512/x hash function - * cores. - * - * Note: This version of the program talks to the FPGA over an EIM bus. - * - * The single and dual block test cases are taken from the - * NIST KAT document: - * http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf - * - * - * Authors: Joachim Strömbergson, Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tc_eim.h" -#include "cryptech_memory_map.h" - -int debug = 0; -int quiet = 0; -int repeat = 0; - - -/* SHA-1/SHA-256 One Block Message Sample - Input Message: "abc" */ -const uint8_t NIST_512_SINGLE[] = -{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; - -const uint8_t SHA1_SINGLE_DIGEST[] = -{ 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, - 0xba, 0x3e, 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, - 0x9c, 0xd0, 0xd8, 0x9d }; - -const uint8_t SHA256_SINGLE_DIGEST[] = -{ 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, - 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, - 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, - 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }; - -/* SHA-1/SHA-256 Two Block Message Sample - Input Message: "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" */ -const uint8_t NIST_512_DOUBLE0[] = -{ 0x61, 0x62, 0x63, 0x64, 0x62, 0x63, 0x64, 0x65, - 0x63, 0x64, 0x65, 0x66, 0x64, 0x65, 0x66, 0x67, - 0x65, 0x66, 0x67, 0x68, 0x66, 0x67, 0x68, 0x69, - 0x67, 0x68, 0x69, 0x6A, 0x68, 0x69, 0x6A, 0x6B, - 0x69, 0x6A, 0x6B, 0x6C, 0x6A, 0x6B, 0x6C, 0x6D, - 0x6B, 0x6C, 0x6D, 0x6E, 0x6C, 0x6D, 0x6E, 0x6F, - 0x6D, 0x6E, 0x6F, 0x70, 0x6E, 0x6F, 0x70, 0x71, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -const uint8_t NIST_512_DOUBLE1[] = -{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0 }; - -const uint8_t SHA1_DOUBLE_DIGEST[] = -{ 0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, - 0xBA, 0xAE, 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, - 0xE5, 0x46, 0x70, 0xF1 }; - -const uint8_t SHA256_DOUBLE_DIGEST[] = -{ 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, - 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, - 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, - 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }; - -/* SHA-512 One Block Message Sample - Input Message: "abc" */ -const uint8_t NIST_1024_SINGLE[] = -{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; - -const uint8_t SHA512_224_SINGLE_DIGEST[] = -{ 0x46, 0x34, 0x27, 0x0f, 0x70, 0x7b, 0x6a, 0x54, - 0xda, 0xae, 0x75, 0x30, 0x46, 0x08, 0x42, 0xe2, - 0x0e, 0x37, 0xed, 0x26, 0x5c, 0xee, 0xe9, 0xa4, - 0x3e, 0x89, 0x24, 0xaa }; -const uint8_t SHA512_256_SINGLE_DIGEST[] = -{ 0x53, 0x04, 0x8e, 0x26, 0x81, 0x94, 0x1e, 0xf9, - 0x9b, 0x2e, 0x29, 0xb7, 0x6b, 0x4c, 0x7d, 0xab, - 0xe4, 0xc2, 0xd0, 0xc6, 0x34, 0xfc, 0x6d, 0x46, - 0xe0, 0xe2, 0xf1, 0x31, 0x07, 0xe7, 0xaf, 0x23 }; -const uint8_t SHA384_SINGLE_DIGEST[] = -{ 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, - 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07, - 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, - 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, - 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23, - 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 }; -const uint8_t SHA512_SINGLE_DIGEST[] = -{ 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, - 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, - 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, - 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, - 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8, - 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, - 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, - 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f }; - -/* SHA-512 Two Block Message Sample - Input Message: "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" - "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" */ -const uint8_t NIST_1024_DOUBLE0[] = -{ 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, - 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, - 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, - 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, - 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, - 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, - 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, - 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, - 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, - 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, - 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, - 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -const uint8_t NIST_1024_DOUBLE1[] = -{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80 }; - -const uint8_t SHA512_224_DOUBLE_DIGEST[] = -{ 0x23, 0xfe, 0xc5, 0xbb, 0x94, 0xd6, 0x0b, 0x23, - 0x30, 0x81, 0x92, 0x64, 0x0b, 0x0c, 0x45, 0x33, - 0x35, 0xd6, 0x64, 0x73, 0x4f, 0xe4, 0x0e, 0x72, - 0x68, 0x67, 0x4a, 0xf9 }; -const uint8_t SHA512_256_DOUBLE_DIGEST[] = -{ 0x39, 0x28, 0xe1, 0x84, 0xfb, 0x86, 0x90, 0xf8, - 0x40, 0xda, 0x39, 0x88, 0x12, 0x1d, 0x31, 0xbe, - 0x65, 0xcb, 0x9d, 0x3e, 0xf8, 0x3e, 0xe6, 0x14, - 0x6f, 0xea, 0xc8, 0x61, 0xe1, 0x9b, 0x56, 0x3a }; -const uint8_t SHA384_DOUBLE_DIGEST[] = -{ 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8, - 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47, - 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2, - 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12, - 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9, - 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 }; -const uint8_t SHA512_DOUBLE_DIGEST[] = -{ 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda, - 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f, - 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1, - 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18, - 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4, - 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a, - 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54, - 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 }; - -/* ---------------- sanity test case ---------------- */ - -int TC0() -{ - uint8_t board_name0[4] = "PVT1"; - uint8_t board_name1[4] = " "; - uint8_t board_version[4] = "0.10"; - - uint8_t comm_name0[4] = "eim "; - uint8_t comm_name1[4] = " "; - uint8_t comm_version[4] = "0.10"; - - uint8_t t[4]; - - if (!quiet) - printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); - - /* write current time into dummy register, then try to read it back - * to make sure that we can actually write something into EIM - */ - (void)time((time_t *)t); - if (tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4) != 0) - return 1; - - if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || - tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || - tc_expected(BOARD_ADDR_VERSION, board_version, 4) || - tc_expected(BOARD_ADDR_DUMMY, (void *)t, 4)) - return 1; - - if (!quiet) - printf("TC0-2: Reading name and version words from communications core.\n"); - - return - tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || - tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || - tc_expected(COMM_ADDR_VERSION, comm_version, 4); -} - -/* ---------------- SHA-1 test cases ---------------- */ - -/* TC1: Read name and version from SHA-1 core. */ -int TC1(void) -{ - uint8_t name0[4] = "sha1"; - uint8_t name1[4] = " "; - uint8_t version[4] = "0.50"; - - if (!quiet) - printf("TC1: Reading name and version words from SHA-1 core.\n"); - - return - tc_expected(SHA1_ADDR_NAME0, name0, 4) || - tc_expected(SHA1_ADDR_NAME1, name1, 4) || - tc_expected(SHA1_ADDR_VERSION, version, 4); -} - -/* TC2: SHA-1 Single block message test as specified by NIST. */ -int TC2(void) -{ - const uint8_t *block = NIST_512_SINGLE; - const uint8_t *expected = SHA1_SINGLE_DIGEST; - int ret; - - if (!quiet) - printf("TC2: Single block message test for SHA-1.\n"); - - /* Write block to SHA-1. */ - tc_write(SHA1_ADDR_BLOCK, block, SHA1_BLOCK_LEN); - /* Start initial block hashing, wait and check status. */ - tc_init(SHA1_ADDR_CTRL); - tc_wait_valid(SHA1_ADDR_STATUS); - /* Extract the digest. */ - ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); - return ret; -} - -/* TC3: SHA-1 Double block message test as specified by NIST. */ -int TC3(void) -{ - const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; - static const uint8_t block0_expected[] = - { 0xF4, 0x28, 0x68, 0x18, 0xC3, 0x7B, 0x27, 0xAE, - 0x04, 0x08, 0xF5, 0x81, 0x84, 0x67, 0x71, 0x48, - 0x4A, 0x56, 0x65, 0x72 }; - const uint8_t *expected = SHA1_DOUBLE_DIGEST; - int ret; - - if (!quiet) - printf("TC3: Double block message test for SHA-1.\n"); - - /* Write first block to SHA-1. */ - tc_write(SHA1_ADDR_BLOCK, block[0], SHA1_BLOCK_LEN); - /* Start initial block hashing, wait and check status. */ - tc_init(SHA1_ADDR_CTRL); - tc_wait_valid(SHA1_ADDR_STATUS); - /* Extract the first digest. */ - tc_expected(SHA1_ADDR_DIGEST, block0_expected, SHA1_DIGEST_LEN); - /* Write second block to SHA-1. */ - tc_write(SHA1_ADDR_BLOCK, block[1], SHA1_BLOCK_LEN); - /* Start next block hashing, wait and check status. */ - tc_next(SHA1_ADDR_CTRL); - tc_wait_valid(SHA1_ADDR_STATUS); - /* Extract the second digest. */ - ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); - return ret; -} - -/* ---------------- SHA-256 test cases ---------------- */ - -/* TC4: Read name and version from SHA-256 core. */ -int TC4(void) -{ - uint8_t name0[4] = "sha2"; - uint8_t name1[4] = "-256"; - uint8_t version[4] = "0.80"; - - if (!quiet) - printf("TC4: Reading name, type and version words from SHA-256 core.\n"); - - return - tc_expected(SHA256_ADDR_NAME0, name0, 4) || - tc_expected(SHA256_ADDR_NAME1, name1, 4) || - tc_expected(SHA256_ADDR_VERSION, version, 4); -} - -/* TC5: SHA-256 Single block message test as specified by NIST. */ -int TC5() -{ - const uint8_t *block = NIST_512_SINGLE; - const uint8_t *expected = SHA256_SINGLE_DIGEST; - - if (!quiet) - printf("TC5: Single block message test for SHA-256.\n"); - - return - /* Write block to SHA-256. */ - tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_init(SHA256_ADDR_CTRL) || - tc_wait_valid(SHA256_ADDR_STATUS) || - /* Extract the digest. */ - tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); -} - -/* TC6: SHA-256 Double block message test as specified by NIST. */ -int TC6() -{ - const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; - static const uint8_t block0_expected[] = - { 0x85, 0xE6, 0x55, 0xD6, 0x41, 0x7A, 0x17, 0x95, - 0x33, 0x63, 0x37, 0x6A, 0x62, 0x4C, 0xDE, 0x5C, - 0x76, 0xE0, 0x95, 0x89, 0xCA, 0xC5, 0xF8, 0x11, - 0xCC, 0x4B, 0x32, 0xC1, 0xF2, 0x0E, 0x53, 0x3A }; - const uint8_t *expected = SHA256_DOUBLE_DIGEST; - - if (!quiet) - printf("TC6: Double block message test for SHA-256.\n"); - - return - /* Write first block to SHA-256. */ - tc_write(SHA256_ADDR_BLOCK, block[0], SHA256_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_init(SHA256_ADDR_CTRL) || - tc_wait_valid(SHA256_ADDR_STATUS) || - /* Extract the first digest. */ - tc_expected(SHA256_ADDR_DIGEST, block0_expected, SHA256_DIGEST_LEN) || - /* Write second block to SHA-256. */ - tc_write(SHA256_ADDR_BLOCK, block[1], SHA256_BLOCK_LEN) || - /* Start next block hashing, wait and check status. */ - tc_next(SHA256_ADDR_CTRL) || - tc_wait_valid(SHA256_ADDR_STATUS) || - /* Extract the second digest. */ - tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); -} - -/* TC7: SHA-256 Huge message test. */ -int TC7() -{ - static const uint8_t block[] = - { 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, - 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, - 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, - 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f }; - - /* final digest after 1000 iterations */ - static const uint8_t expected[] = - { 0x76, 0x38, 0xf3, 0xbc, 0x50, 0x0d, 0xd1, 0xa6, - 0x58, 0x6d, 0xd4, 0xd0, 0x1a, 0x15, 0x51, 0xaf, - 0xd8, 0x21, 0xd2, 0x35, 0x2f, 0x91, 0x9e, 0x28, - 0xd5, 0x84, 0x2f, 0xab, 0x03, 0xa4, 0x0f, 0x2a }; - - int i, n = 1000; - - if (!quiet) - printf("TC7: Message with %d blocks test for SHA-256.\n", n); - - /* Write block data to SHA-256. */ - if (tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN)) - return 1; - - /* Start initial block hashing, wait and check status. */ - if (tc_init(SHA256_ADDR_CTRL) || - tc_wait_ready(SHA256_ADDR_STATUS)) - return 1; - - /* First block done. Do the rest. */ - for (i = 1; i < n; ++i) { - /* Start next block hashing, wait and check status. */ - if (tc_next(SHA256_ADDR_CTRL) || - tc_wait_ready(SHA256_ADDR_STATUS)) - return 1; - } - - /* XXX valid is probably set at the same time as ready */ - if (tc_wait_valid(SHA256_ADDR_STATUS)) - return 1; - /* Extract the final digest. */ - return tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); -} - -/* ---------------- SHA-512 test cases ---------------- */ - -/* TC8: Read name and version from SHA-512 core. */ -int TC8() -{ - uint8_t name0[4] = "sha2"; - uint8_t name1[4] = "-512"; - uint8_t version[4] = "0.80"; - - if (!quiet) - printf("TC8: Reading name, type and version words from SHA-512 core.\n"); - - return - tc_expected(SHA512_ADDR_NAME0, name0, 4) || - tc_expected(SHA512_ADDR_NAME1, name1, 4) || - tc_expected(SHA512_ADDR_VERSION, version, 4); -} - -/* TC9: SHA-512 Single block message test as specified by NIST. - We do this for all modes. */ -int tc9(int mode, const uint8_t *expected, int digest_len) -{ - const uint8_t *block = NIST_1024_SINGLE; - uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; - - return - /* Write block to SHA-512. */ - tc_write(SHA512_ADDR_BLOCK, block, SHA512_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_write(SHA512_ADDR_CTRL, init, 4) || - tc_wait_valid(SHA512_ADDR_STATUS) || - /* Extract the digest. */ - tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); -} - -int TC9() -{ - if (!quiet) - printf("TC9-1: Single block message test for SHA-512/224.\n"); - if (tc9(MODE_SHA_512_224, SHA512_224_SINGLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC9-2: Single block message test for SHA-512/256.\n"); - if (tc9(MODE_SHA_512_256, SHA512_256_SINGLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC9-3: Single block message test for SHA-384.\n"); - if (tc9(MODE_SHA_384, SHA384_SINGLE_DIGEST, SHA384_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC9-4: Single block message test for SHA-512.\n"); - if (tc9(MODE_SHA_512, SHA512_SINGLE_DIGEST, SHA512_DIGEST_LEN) != 0) - return 1; - - return 0; -} - -/* TC10: SHA-512 Double block message test as specified by NIST. - We do this for all modes. */ -int tc10(int mode, const uint8_t *expected, int digest_len) -{ - const uint8_t *block[2] = { NIST_1024_DOUBLE0, NIST_1024_DOUBLE1 }; - uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; - uint8_t next[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode }; - - return - /* Write first block to SHA-512. */ - tc_write(SHA512_ADDR_BLOCK, block[0], SHA512_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_write(SHA512_ADDR_CTRL, init, 4) || - tc_wait_ready(SHA512_ADDR_STATUS) || - /* Write second block to SHA-512. */ - tc_write(SHA512_ADDR_BLOCK, block[1], SHA512_BLOCK_LEN) || - /* Start next block hashing, wait and check status. */ - tc_write(SHA512_ADDR_CTRL, next, 4) || - tc_wait_valid(SHA512_ADDR_STATUS) || - /* Extract the digest. */ - tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); -} - -int TC10() -{ - if (!quiet) - printf("TC10-1: Double block message test for SHA-512/224.\n"); - if (tc10(MODE_SHA_512_224, SHA512_224_DOUBLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC10-2: Double block message test for SHA-512/256.\n"); - if (tc10(MODE_SHA_512_256, SHA512_256_DOUBLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC10-3: Double block message test for SHA-384.\n"); - if (tc10(MODE_SHA_384, SHA384_DOUBLE_DIGEST, SHA384_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC10-4: Double block message test for SHA-512.\n"); - if (tc10(MODE_SHA_512, SHA512_DOUBLE_DIGEST, SHA512_DIGEST_LEN) != 0) - return 1; - - return 0; -} - -/* ---------------- main ---------------- */ - -/* signal handler for ctrl-c to end repeat testing */ -unsigned long iter = 0; -struct timeval tv_start, tv_end; -void sighandler(int unused) -{ - double tv_diff; - - gettimeofday(&tv_end, NULL); - tv_diff = (double)(tv_end.tv_sec - tv_start.tv_sec) + - (double)(tv_end.tv_usec - tv_start.tv_usec)/1000000; - printf("\n%lu iterations in %.3f seconds (%.3f iterations/sec)\n", - iter, tv_diff, (double)iter/tv_diff); - exit(EXIT_SUCCESS); -} - -int main(int argc, char *argv[]) -{ - typedef int (*tcfp)(void); - tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7, TC8, TC9, TC10 }; - tcfp sha1_tests[] = { TC1, TC2, TC3 }; - tcfp sha256_tests[] = { TC4, TC5, TC6, TC7 }; - tcfp sha512_tests[] = { TC8, TC9, TC10 }; - - char *usage = "Usage: %s [-h] [-d] [-q] [-r] tc...\n"; - int i, j, opt; - - while ((opt = getopt(argc, argv, "h?dqr")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'd': - debug = 1; - break; - case 'q': - quiet = 1; - break; - case 'r': - repeat = 1; - break; - default: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - - /* repeat one test until interrupted */ - if (repeat) { - tcfp tc; - if (optind != argc - 1) { - fprintf(stderr, "only one test case can be repeated\n"); - return EXIT_FAILURE; - } - j = atoi(argv[optind]); - if (j < 0 || j >= sizeof(all_tests)/sizeof(all_tests[0])) { - fprintf(stderr, "invalid test number %s\n", argv[optind]); - return EXIT_FAILURE; - } - tc = (all_tests[j]); - srand(time(NULL)); - signal(SIGINT, sighandler); - gettimeofday(&tv_start, NULL); - while (1) { - ++iter; - if ((iter & 0xffff) == 0) { - printf("."); - fflush(stdout); - } - if (tc() != 0) - sighandler(0); - } - return EXIT_SUCCESS; /*NOTREACHED*/ - } - - /* no args == run all tests */ - if (optind >= argc) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - return EXIT_SUCCESS; - } - - /* run one or more tests (by number) or groups of tests (by name) */ - for (i = optind; i < argc; ++i) { - if (strcmp(argv[i], "all") == 0) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (strcmp(argv[i], "sha1") == 0) { - for (j = 0; j < sizeof(sha1_tests)/sizeof(sha1_tests[0]); ++j) - if (sha1_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (strcmp(argv[i], "sha256") == 0) { - for (j = 0; j < sizeof(sha256_tests)/sizeof(sha256_tests[0]); ++j) - if (sha256_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (strcmp(argv[i], "sha512") == 0) { - for (j = 0; j < sizeof(sha512_tests)/sizeof(sha512_tests[0]); ++j) - if (sha512_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (isdigit(argv[i][0]) && - (((j = atoi(argv[i])) >= 0) && - (j < sizeof(all_tests)/sizeof(all_tests[0])))) { - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else { - fprintf(stderr, "unknown test case %s\n", argv[i]); - return EXIT_FAILURE; - } - } - - return EXIT_SUCCESS; -} diff --git a/eim/sw/novena-eim.c b/eim/sw/novena-eim.c deleted file mode 100644 index 85bfac0..0000000 --- a/eim/sw/novena-eim.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * novena-eim.c - * ------------ - * This module contains the userland magic to set up and use the EIM bus. - * - * - * Author: Pavel Shatov - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include -#include -#include -#include -#include -#include -#include - -#include "novena-eim.h" - - -//------------------------------------------------------------------------------ -// Defines -//------------------------------------------------------------------------------ -#define MEMORY_DEVICE "/dev/mem" - -#define IOMUXC_MUX_MODE_ALT0 0 // 000 - -#define IOMUXC_PAD_CTL_SRE_FAST 1 // 1 -#define IOMUXC_PAD_CTL_DSE_33_OHM 7 // 111 -#define IOMUXC_PAD_CTL_SPEED_MEDIUM_10 2 // 10 -#define IOMUXC_PAD_CTL_ODE_DISABLED 0 // 0 -#define IOMUXC_PAD_CTL_PKE_DISABLED 0 // 0 -#define IOMUXC_PAD_CTL_PUE_PULL 1 // 1 -#define IOMUXC_PAD_CTL_PUS_100K_OHM_PU 2 // 10 -#define IOMUXC_PAD_CTL_HYS_DISABLED 0 // 0 - -#define CCM_CGR_OFF 0 // 00 -#define CCM_CGR_ON_EXCEPT_STOP 3 // 11 - - -//------------------------------------------------------------------------------ -// CPU Registers -//------------------------------------------------------------------------------ -enum IMX6DQ_REGISTER_OFFSET -{ - IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B = 0x020E00F8, - IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B = 0x020E0100, - IOMUXC_SW_MUX_CTL_PAD_EIM_RW = 0x020E0104, - IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B = 0x020E0108, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 = 0x020E0114, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 = 0x020E0118, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 = 0x020E011C, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 = 0x020E0120, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 = 0x020E0124, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 = 0x020E0128, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 = 0x020E012C, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 = 0x020E0130, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 = 0x020E0134, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 = 0x020E0138, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 = 0x020E013C, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 = 0x020E0140, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 = 0x020E0144, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 = 0x020E0148, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 = 0x020E014C, - IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 = 0x020E0150, - IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B = 0x020E0154, - IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK = 0x020E0158, - - IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B = 0x020E040C, - IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B = 0x020E0414, - IOMUXC_SW_PAD_CTL_PAD_EIM_RW = 0x020E0418, - IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B = 0x020E041C, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 = 0x020E0428, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 = 0x020E042C, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 = 0x020E0430, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 = 0x020E0434, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 = 0x020E0438, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 = 0x020E043C, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 = 0x020E0440, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 = 0x020E0444, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 = 0x020E0448, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 = 0x020E044C, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 = 0x020E0450, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 = 0x020E0454, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 = 0x020E0458, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 = 0x020E045C, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 = 0x020E0460, - IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 = 0x020E0464, - IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B = 0x020E0468, - IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK = 0x020E046C, - - CCM_CCGR6 = 0x020C4080, - - EIM_CS0GCR1 = 0x021B8000, - EIM_CS0GCR2 = 0x021B8004, - EIM_CS0RCR1 = 0x021B8008, - EIM_CS0RCR2 = 0x021B800C, - EIM_CS0WCR1 = 0x021B8010, - EIM_CS0WCR2 = 0x021B8014, - - EIM_WCR = 0x021B8090, - EIM_WIAR = 0x021B8094, - EIM_EAR = 0x021B8098, -}; - - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ -struct IOMUXC_SW_MUX_CTL_PAD_EIM -{ - unsigned int mux_mode : 3; - unsigned int reserved_3 : 1; - unsigned int sion : 1; - unsigned int reserved_31_5 : 27; -}; - -struct IOMUXC_SW_PAD_CTL_PAD_EIM -{ - unsigned int sre : 1; - unsigned int reserved_2_1 : 2; - unsigned int dse : 3; - unsigned int speed : 2; - unsigned int reserved_10_8 : 3; - unsigned int ode : 1; - unsigned int pke : 1; - unsigned int pue : 1; - unsigned int pus : 2; - unsigned int hys : 1; - unsigned int reserved_31_17 : 15; -}; - -struct CCM_CCGR6 -{ - unsigned int cg0_usboh3 : 2; - unsigned int cg1_usdhc1 : 2; - unsigned int cg2_usdhc2 : 2; - unsigned int cg3_usdhc3 : 2; - - unsigned int cg3_usdhc4 : 2; - unsigned int cg5_eim_slow : 2; - unsigned int cg6_vdoaxiclk : 2; - unsigned int cg7_vpu : 2; - - unsigned int cg8_reserved : 2; - unsigned int cg9_reserved : 2; - unsigned int cg10_reserved : 2; - unsigned int cg11_reserved : 2; - - unsigned int cg12_reserved : 2; - unsigned int cg13_reserved : 2; - unsigned int cg14_reserved : 2; - unsigned int cg15_reserved : 2; -}; - -struct EIM_CS_GCR1 -{ - unsigned int csen : 1; - unsigned int swr : 1; - unsigned int srd : 1; - unsigned int mum : 1; - unsigned int wfl : 1; - unsigned int rfl : 1; - unsigned int cre : 1; - unsigned int crep : 1; - unsigned int bl : 3; - unsigned int wc : 1; - unsigned int bcd : 2; - unsigned int bcs : 2; - unsigned int dsz : 3; - unsigned int sp : 1; - unsigned int csrec : 3; - unsigned int aus : 1; - unsigned int gbc : 3; - unsigned int wp : 1; - unsigned int psz : 4; -}; - -struct EIM_CS_GCR2 -{ - unsigned int adh : 2; - unsigned int reserved_3_2 : 2; - unsigned int daps : 4; - unsigned int dae : 1; - unsigned int dap : 1; - unsigned int reserved_11_10 : 2; - unsigned int mux16_byp_grant : 1; - unsigned int reserved_31_13 : 19; -}; - -struct EIM_CS_RCR1 -{ - unsigned int rcsn : 3; - unsigned int reserved_3 : 1; - unsigned int rcsa : 3; - unsigned int reserved_7 : 1; - unsigned int oen : 3; - unsigned int reserved_11 : 1; - unsigned int oea : 3; - unsigned int reserved_15 : 1; - unsigned int radvn : 3; - unsigned int ral : 1; - unsigned int radva : 3; - unsigned int reserved_23 : 1; - unsigned int rwsc : 6; - unsigned int reserved_31_30 : 2; -}; - -struct EIM_CS_RCR2 -{ - unsigned int rben : 3; - unsigned int rbe : 1; - unsigned int rbea : 3; - unsigned int reserved_7 : 1; - unsigned int rl : 2; - unsigned int reserved_11_10 : 2; - unsigned int pat : 3; - unsigned int apr : 1; - unsigned int reserved_31_16 : 16; -}; - -struct EIM_CS_WCR1 -{ - unsigned int wcsn : 3; - unsigned int wcsa : 3; - unsigned int wen : 3; - unsigned int wea : 3; - unsigned int wben : 3; - unsigned int wbea : 3; - unsigned int wadvn : 3; - unsigned int wadva : 3; - unsigned int wwsc : 6; - unsigned int wbed : 1; - unsigned int wal : 1; -}; - -struct EIM_CS_WCR2 -{ - unsigned int wbcdd : 1; - unsigned int reserved_31_1 : 31; -}; - -struct EIM_WCR -{ - unsigned int bcm : 1; - unsigned int gbcd : 2; - unsigned int reserved_3 : 1; - unsigned int inten : 1; - unsigned int intpol : 1; - unsigned int reserved_7_6 : 2; - unsigned int wdog_en : 1; - unsigned int wdog_limit : 2; - unsigned int reserved_31_11 : 21; -}; - -struct EIM_WIAR -{ - unsigned int ips_req : 1; - unsigned int ips_ack : 1; - unsigned int irq : 1; - unsigned int errst : 1; - unsigned int aclk_en : 1; - unsigned int reserved_31_5 : 27; -}; - -struct EIM_EAR -{ - unsigned int error_addr : 32; -}; - - -//------------------------------------------------------------------------------ -// Variables -//------------------------------------------------------------------------------ -static long mem_page_size = 0; -static int mem_dev_fd = -1; -static void * mem_map_ptr = MAP_FAILED; -static off_t mem_base_addr = 0; - - -//------------------------------------------------------------------------------ -// Prototypes -//------------------------------------------------------------------------------ -static void _eim_setup_iomuxc (void); -static void _eim_setup_ccm (void); -static void _eim_setup_eim (void); -static void _eim_cleanup (void); -static off_t _eim_calc_offset (off_t); -static void _eim_remap_mem (off_t); - - -//------------------------------------------------------------------------------ -// Set up EIM bus. Returns 0 on success, -1 on failure. -//------------------------------------------------------------------------------ -int eim_setup(void) -{ - // register cleanup function - if (atexit(_eim_cleanup) != 0) { - fprintf(stderr, "ERROR: atexit() failed.\n"); - return -1; - } - - // determine memory page size to use in mmap() - mem_page_size = sysconf(_SC_PAGESIZE); - if (mem_page_size < 1) { - fprintf(stderr, "ERROR: sysconf(_SC_PAGESIZE) == %ld\n", mem_page_size); - return -1; - } - - // try to open memory device - mem_dev_fd = open(MEMORY_DEVICE, O_RDWR | O_SYNC); - if (mem_dev_fd == -1) { - fprintf(stderr, "ERROR: open(%s) failed.\n", MEMORY_DEVICE); - return -1; - } - - // configure IOMUXC - _eim_setup_iomuxc(); - - // configure Clock Controller Module - _eim_setup_ccm(); - - /* We need to properly configure EIM mode and all the corresponding parameters. - * That's a lot of code, let's do it now. - */ - _eim_setup_eim(); - - // done - return 0; -} - - -//------------------------------------------------------------------------------ -// Shut down EIM bus. This is called automatically on exit(). -//------------------------------------------------------------------------------ -static void _eim_cleanup(void) -{ - // unmap memory if needed - if (mem_map_ptr != MAP_FAILED) - if (munmap(mem_map_ptr, mem_page_size) != 0) - fprintf(stderr, "WARNING: munmap() failed.\n"); - - // close memory device if needed - if (mem_dev_fd != -1) - if (close(mem_dev_fd) != 0) - fprintf(stderr, "WARNING: close() failed.\n"); -} - - -//------------------------------------------------------------------------------ -// Several blocks in the CPU have common pins. We use the I/O MUX Controller -// to configure what block will actually use I/O pins. We wait for the EIM -// module to be able to communicate with the on-board FPGA. -//------------------------------------------------------------------------------ -static void _eim_setup_iomuxc(void) -{ - // create structures - struct IOMUXC_SW_MUX_CTL_PAD_EIM reg_mux; // mux control register - struct IOMUXC_SW_PAD_CTL_PAD_EIM reg_pad; // pad control register - - // setup mux control register - reg_mux.mux_mode = IOMUXC_MUX_MODE_ALT0; // ALT0 mode must be used for EIM - reg_mux.sion = 0; // forced input not needed - reg_mux.reserved_3 = 0; // must be 0 - reg_mux.reserved_31_5 = 0; // must be 0 - - // setup pad control register - reg_pad.sre = IOMUXC_PAD_CTL_SRE_FAST; // fast slew rate - reg_pad.dse = IOMUXC_PAD_CTL_DSE_33_OHM; // highest drive strength - reg_pad.speed = IOMUXC_PAD_CTL_SPEED_MEDIUM_10; // medium speed - reg_pad.ode = IOMUXC_PAD_CTL_ODE_DISABLED; // open drain not needed - reg_pad.pke = IOMUXC_PAD_CTL_PKE_DISABLED; // neither pull nor keeper are needed - reg_pad.pue = IOMUXC_PAD_CTL_PUE_PULL; // doesn't matter actually, because PKE is disabled - reg_pad.pus = IOMUXC_PAD_CTL_PUS_100K_OHM_PU; // doesn't matter actually, because PKE is disabled - reg_pad.hys = IOMUXC_PAD_CTL_HYS_DISABLED; // use CMOS, not Schmitt trigger input - reg_pad.reserved_2_1 = 0; // must be 0 - reg_pad.reserved_10_8 = 0; // must be 0 - reg_pad.reserved_31_17 = 0; // must be 0 - - // all the pins must be configured to use the same ALT0 mode - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_RW, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD00, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD01, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD02, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD03, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD04, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD05, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD06, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD07, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD08, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD09, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD10, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD11, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD12, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD13, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD14, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD15, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B, (uint32_t *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK, (uint32_t *)®_mux); - - // we need to configure all the I/O pads too - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_RW, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B, (uint32_t *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, (uint32_t *)®_pad); -} - - -//------------------------------------------------------------------------------ -// Configure Clock Controller Module to enable clocking of EIM block. -//------------------------------------------------------------------------------ -static void _eim_setup_ccm(void) -{ - // create structure - struct CCM_CCGR6 ccm_ccgr6; - - // read register - eim_read_32(CCM_CCGR6, (uint32_t *)&ccm_ccgr6); - - // modify register - ccm_ccgr6.cg0_usboh3 = CCM_CGR_ON_EXCEPT_STOP; - ccm_ccgr6.cg1_usdhc1 = CCM_CGR_OFF; - ccm_ccgr6.cg2_usdhc2 = CCM_CGR_ON_EXCEPT_STOP; - ccm_ccgr6.cg3_usdhc3 = CCM_CGR_ON_EXCEPT_STOP; - - ccm_ccgr6.cg3_usdhc4 = CCM_CGR_OFF; - ccm_ccgr6.cg5_eim_slow = CCM_CGR_ON_EXCEPT_STOP; - ccm_ccgr6.cg6_vdoaxiclk = CCM_CGR_OFF; - ccm_ccgr6.cg7_vpu = CCM_CGR_OFF; - - ccm_ccgr6.cg8_reserved = 0; - ccm_ccgr6.cg9_reserved = 0; - ccm_ccgr6.cg10_reserved = 0; - ccm_ccgr6.cg11_reserved = 0; - ccm_ccgr6.cg12_reserved = 0; - ccm_ccgr6.cg13_reserved = 0; - ccm_ccgr6.cg14_reserved = 0; - ccm_ccgr6.cg15_reserved = 0; - - // write register - eim_write_32(CCM_CCGR6, (uint32_t *)&ccm_ccgr6); -} - - -//------------------------------------------------------------------------------ -// Configure EIM mode and all the corresponding parameters. That's a lot of code. -//------------------------------------------------------------------------------ -static void _eim_setup_eim(void) -{ - // create structures - struct EIM_CS_GCR1 gcr1; - struct EIM_CS_GCR2 gcr2; - struct EIM_CS_RCR1 rcr1; - struct EIM_CS_RCR2 rcr2; - struct EIM_CS_WCR1 wcr1; - struct EIM_CS_WCR2 wcr2; - - struct EIM_WCR wcr; - struct EIM_WIAR wiar; - struct EIM_EAR ear; - - // read all the registers - eim_read_32(EIM_CS0GCR1, (uint32_t *)&gcr1); - eim_read_32(EIM_CS0GCR2, (uint32_t *)&gcr2); - eim_read_32(EIM_CS0RCR1, (uint32_t *)&rcr1); - eim_read_32(EIM_CS0RCR2, (uint32_t *)&rcr2); - eim_read_32(EIM_CS0WCR1, (uint32_t *)&wcr1); - eim_read_32(EIM_CS0WCR2, (uint32_t *)&wcr2); - - eim_read_32(EIM_WCR, (uint32_t *)&wcr); - eim_read_32(EIM_WIAR, (uint32_t *)&wiar); - eim_read_32(EIM_EAR, (uint32_t *)&ear); - - // manipulate registers as needed - gcr1.csen = 1; // chip select is enabled - gcr1.swr = 1; // write is sync - gcr1.srd = 1; // read is sync - gcr1.mum = 1; // address and data are multiplexed - gcr1.wfl = 0; // write latency is not fixed - gcr1.rfl = 0; // read latency is not fixed - gcr1.cre = 0; // CRE signal not needed - //gcr1.crep = x; // don't care, CRE not used - gcr1.bl = 4; // burst length - gcr1.wc = 0; // write is not continuous - gcr1.bcd = 3; // BCLK divisor is 3+1=4 - gcr1.bcs = 1; // delay from ~CS to BCLK is 1 cycle - gcr1.dsz = 1; // 16 bits per databeat at DATA[15:0] - gcr1.sp = 0; // supervisor protection is disabled - gcr1.csrec = 1; // ~CS recovery is 1 cycle - gcr1.aus = 1; // address is not shifted - gcr1.gbc = 1; // ~CS gap is 1 cycle - gcr1.wp = 0; // write protection is not enabled - //gcr1.psz = x; // don't care, page mode is not used - - gcr2.adh = 0; // address hold duration is 1 cycle - //gcr2.daps = x; // don't care, DTACK is not used - gcr2.dae = 0; // DTACK is not used - //gcr2.dap = x; // don't care, DTACK is not used - gcr2.mux16_byp_grant= 1; // enable grant mechanism - gcr2.reserved_3_2 = 0; // must be 0 - gcr2.reserved_11_10 = 0; // must be 0 - gcr2.reserved_31_13 = 0; // must be 0 - - //rcr1.rcsn = x; // don't care in sync mode - rcr1.rcsa = 0; // no delay for ~CS needed - //rcr1.oen = x; // don't care in sync mode - rcr1.oea = 0; // no delay for ~OE needed - rcr1.radvn = 0; // no delay for ~LBA needed - rcr1.ral = 0; // clear ~LBA when needed - rcr1.radva = 0; // no delay for ~LBA needed - rcr1.rwsc = 1; // one wait state - rcr1.reserved_3 = 0; // must be 0 - rcr1.reserved_7 = 0; // must be 0 - rcr1.reserved_11 = 0; // must be 0 - rcr1.reserved_15 = 0; // must be 0 - rcr1.reserved_23 = 0; // must be 0 - rcr1.reserved_31_30 = 0; // must be 0 - - //rcr2.rben = x; // don't care in sync mode - rcr2.rbe = 0; // BE is disabled - //rcr2.rbea = x; // don't care when BE is not used - rcr2.rl = 0; // read latency is 0 - //rcr2.pat = x; // don't care when page read is not used - rcr2.apr = 0; // page read mode is not used - rcr2.reserved_7 = 0; // must be 0 - rcr2.reserved_11_10 = 0; // must be 0 - rcr2.reserved_31_16 = 0; // must be 0 - - //wcr1.wcsn = x; // don't care in sync mode - wcr1.wcsa = 0; // no delay for ~CS needed - //wcr1.wen = x; // don't care in sync mode - wcr1.wea = 0; // no delay for ~WR_N needed - //wcr1.wben = x; // don't care in sync mode - //wcr1.wbea = x; // don't care in sync mode - wcr1.wadvn = 0; // no delay for ~LBA needed - wcr1.wadva = 0; // no delay for ~LBA needed - wcr1.wwsc = 1; // no wait state in needed - wcr1.wbed = 1; // BE is disabled - wcr1.wal = 0; // clear ~LBA when needed - - wcr2.wbcdd = 0; // write clock division is not needed - wcr2.reserved_31_1 = 0; // must be 0 - - wcr.bcm = 0; // clock is only active during access - //wcr.gbcd = x; // don't care when BCM=0 - wcr.inten = 0; // interrupt is not used - //wcr.intpol = x; // don't care when interrupt is not used - wcr.wdog_en = 1; // watchdog is enabled - wcr.wdog_limit = 00; // timeout is 128 BCLK cycles - wcr.reserved_3 = 0; // must be 0 - wcr.reserved_7_6 = 0; // must be 0 - wcr.reserved_31_11 = 0; // must be 0 - - wiar.ips_req = 0; // IPS not needed - wiar.ips_ack = 0; // IPS not needed - //wiar.irq = x; // don't touch - //wiar.errst = x; // don't touch - wiar.aclk_en = 1; // clock is enabled - wiar.reserved_31_5 = 0; // must be 0 - - //ear.error_addr = x; // read-only - - // write modified registers - eim_write_32(EIM_CS0GCR1, (uint32_t *)&gcr1); - eim_write_32(EIM_CS0GCR2, (uint32_t *)&gcr2); - eim_write_32(EIM_CS0RCR1, (uint32_t *)&rcr1); - eim_write_32(EIM_CS0RCR2, (uint32_t *)&rcr2); - eim_write_32(EIM_CS0WCR1, (uint32_t *)&wcr1); - eim_write_32(EIM_CS0WCR2, (uint32_t *)&wcr2); - eim_write_32(EIM_WCR, (uint32_t *)&wcr); - eim_write_32(EIM_WIAR, (uint32_t *)&wiar); -/* eim_write_32(EIM_EAR, (uint32_t *)&ear);*/ -} - - -//------------------------------------------------------------------------------ -// Write a 32-bit word to EIM. -// If EIM is not set up correctly, this will abort with a bus error. -//------------------------------------------------------------------------------ -void eim_write_32(off_t offset, uint32_t *pvalue) -{ - // calculate memory offset - uint32_t *ptr = (uint32_t *)_eim_calc_offset(offset); - - // write data to memory - memcpy(ptr, pvalue, sizeof(uint32_t)); -} - -//------------------------------------------------------------------------------ -// Read a 32-bit word from EIM. -// If EIM is not set up correctly, this will abort with a bus error. -//------------------------------------------------------------------------------ -void eim_read_32(off_t offset, uint32_t *pvalue) -{ - // calculate memory offset - uint32_t *ptr = (uint32_t *)_eim_calc_offset(offset); - - // read data from memory - memcpy(pvalue, ptr, sizeof(uint32_t)); -} - - -//------------------------------------------------------------------------------ -// Calculate an offset into the currently-mapped EIM page. -//------------------------------------------------------------------------------ -static off_t _eim_calc_offset(off_t offset) -{ - // make sure that memory is mapped - if (mem_map_ptr == MAP_FAILED) - _eim_remap_mem(offset); - - // calculate starting and ending addresses of currently mapped page - off_t offset_low = mem_base_addr; - off_t offset_high = mem_base_addr + (mem_page_size - 1); - - // check that offset is in currently mapped page, remap new page otherwise - if ((offset < offset_low) || (offset > offset_high)) - _eim_remap_mem(offset); - - // calculate pointer - return (off_t)mem_map_ptr + (offset - mem_base_addr); -} - - -//------------------------------------------------------------------------------ -// Map in a new EIM page. -//------------------------------------------------------------------------------ -static void _eim_remap_mem(off_t offset) -{ - // unmap old memory page if needed - if (mem_map_ptr != MAP_FAILED) { - if (munmap(mem_map_ptr, mem_page_size) != 0) { - fprintf(stderr, "ERROR: munmap() failed.\n"); - exit(EXIT_FAILURE); - } - } - - // calculate starting address of new page - while (offset % mem_page_size) - offset--; - - // try to map new memory page - mem_map_ptr = mmap(NULL, mem_page_size, PROT_READ | PROT_WRITE, MAP_SHARED, - mem_dev_fd, offset); - if (mem_map_ptr == MAP_FAILED) { - fprintf(stderr, "ERROR: mmap() failed.\n"); - exit(EXIT_FAILURE); - } - - // save last mapped page address - mem_base_addr = offset; -} - - -//------------------------------------------------------------------------------ -// End-of-File -//------------------------------------------------------------------------------ diff --git a/eim/sw/novena-eim.h b/eim/sw/novena-eim.h deleted file mode 100644 index 75613bf..0000000 --- a/eim/sw/novena-eim.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * novena-eim.h - * ------------ - * This module contains the userland magic to set up and use the EIM bus. - * - * - * Author: Pavel Shatov - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#define EIM_BASE_ADDR 0x08000000 - -/* Set up EIM bus. - * Returns 0 on success, -1 on failure. - */ -int eim_setup(void); - -/* Write a 32-bit word to EIM. - * If EIM is not set up correctly, this will abort with a bus error. - */ -void eim_write_32(off_t, uint32_t *); - -/* Read a 32-bit word from EIM. - * If EIM is not set up correctly, this will abort with a bus error. - */ -void eim_read_32(off_t, uint32_t *); diff --git a/eim/sw/tc_eim.c b/eim/sw/tc_eim.c deleted file mode 100644 index d44b685..0000000 --- a/eim/sw/tc_eim.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * tc_eim.c - * -------- - * This module contains common code to talk to the FPGA over the EIM bus. - * - * Author: Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "tc_eim.h" - -extern int debug; -static int inited = 0; - -/* ---------------- EIM low-level code ---------------- */ -static int init(void) -{ - if (inited) - return 0; - - if (eim_setup() != 0) { - fprintf(stderr, "EIM setup failed\n"); - return -1; - } - - inited = 1; - return 0; -} - -/* ---------------- test-case low-level code ---------------- */ - -static void dump(char *label, const uint8_t *buf, size_t len) -{ - if (debug) { - int i; - printf("%s [", label); - for (i = 0; i < len; ++i) - printf(" %02x", buf[i]); - printf(" ]\n"); - } -} - -int tc_write(off_t offset, const uint8_t *buf, size_t len) -{ - if (init() != 0) - return -1; - - dump("write ", buf, len); - - for (; len > 0; offset += 4, buf += 4, len -= 4) { - uint32_t val; - val = htonl(*(uint32_t *)buf); - eim_write_32(offset, &val); - } - - return 0; -} - -int tc_read(off_t offset, uint8_t *buf, size_t len) -{ - uint8_t *rbuf = buf; - int rlen = len; - - if (init() != 0) - return -1; - - for (; rlen > 0; offset += 4, rbuf += 4, rlen -= 4) { - uint32_t val; - eim_read_32(offset, &val); - *(uint32_t *)rbuf = ntohl(val); - } - - dump("read ", buf, len); - - return 0; -} - -int tc_expected(off_t offset, const uint8_t *expected, size_t len) -{ - uint8_t *buf; - int i; - - buf = malloc(len); - if (buf == NULL) { - perror("malloc"); - return 1; - } - dump("expect", expected, len); - - if (tc_read(offset, buf, len) != 0) - goto errout; - - for (i = 0; i < len; ++i) - if (buf[i] != expected[i]) { - fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", - i, expected[i], buf[i]); - goto errout; - } - - free(buf); - return 0; -errout: - free(buf); - return 1; -} - -int tc_init(off_t offset) -{ - uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD }; - - return tc_write(offset, buf, 4); -} - -int tc_next(off_t offset) -{ - uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD }; - - return tc_write(offset, buf, 4); -} - -int tc_wait(off_t offset, uint8_t status, int *count) -{ - uint8_t buf[4]; - int i; - - for (i = 1; ; ++i) { - if (count && (*count > 0) && (i >= *count)) { - fprintf(stderr, "tc_wait timed out\n"); - return 1; - } - if (tc_read(offset, buf, 4) != 0) - return -1; - if (buf[3] & status) { - if (count) - *count = i; - return 0; - } - } -} - -int tc_wait_ready(off_t offset) -{ - int limit = 256; - return tc_wait(offset, STATUS_READY_BIT, &limit); -} - -int tc_wait_valid(off_t offset) -{ - int limit = 256; - return tc_wait(offset, STATUS_VALID_BIT, &limit); -} diff --git a/eim/sw/tc_eim.h b/eim/sw/tc_eim.h deleted file mode 100644 index 5da18e4..0000000 --- a/eim/sw/tc_eim.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * tc_eim.h - * -------- - * This module contains common code to talk to the FPGA over the EIM bus. - * - * Author: Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "novena-eim.h" -#define BASE_ADDR EIM_BASE_ADDR -#define SEGMENT_SIZE 0x10000 -#define ADDR(x) (x << 2) -#include "cryptech_memory_map.h" - -/* test case public functions */ -int tc_write(off_t offset, const uint8_t *buf, size_t len); -int tc_read(off_t offset, uint8_t *buf, size_t len); -int tc_expected(off_t offset, const uint8_t *expected, size_t len); -int tc_init(off_t offset); -int tc_next(off_t offset); -int tc_wait(off_t offset, uint8_t status, int *count); -int tc_wait_ready(off_t offset); -int tc_wait_valid(off_t offset); diff --git a/eim/sw/trng_extractor_eim.c b/eim/sw/trng_extractor_eim.c deleted file mode 100644 index be6ab16..0000000 --- a/eim/sw/trng_extractor_eim.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * trng_extractor.c - * ---------------- - * This program extracts raw data from the avalanche_entropy, rosc_entropy, - * and csprng cores. - * - * Author: Paul Selkirk - * Copyright (c) 2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "tc_eim.h" -#include "cryptech_memory_map.h" - -char *usage = -"%s [-a|r|c] [-n #] [-o file]\n\ -\n\ --a avalanche entropy\n\ --r rosc entropy\n\ --c csprng (default data source)\n\ --n number of 4-byte samples (scale with K, M, or G suffix)\n\ --o output file (defaults to stdout)\n\ -"; - -int debug = 0; /* for dump() */ - -/* extract one data sample */ -static int extract(off_t status_addr, off_t data_addr, uint32_t *data) -{ - if (tc_wait(status_addr, ENTROPY1_STATUS_VALID, NULL) != 0) { - fprintf(stderr, "tc_wait failed\n"); - return 1; - } - - if (tc_read(data_addr, (uint8_t *)data, 4) != 0) { - fprintf(stderr, "tc_read failed\n"); - return 1; - } - - return 0; -} - -/* main */ -int main(int argc, char *argv[]) -{ - int i, opt; - unsigned long num_words = 1; - char *endptr; - off_t status_addr = CSPRNG_ADDR_STATUS; - off_t data_addr = CSPRNG_ADDR_RANDOM; - FILE *output = stdout; - uint32_t data; - - /* parse command line */ - while ((opt = getopt(argc, argv, "h?arcn:o:")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'a': - status_addr = ENTROPY1_ADDR_STATUS; - data_addr = ENTROPY1_ADDR_ENTROPY; - break; - case 'r': - status_addr = ENTROPY2_ADDR_STATUS; - data_addr = ENTROPY2_ADDR_ENTROPY; - break; - case 'c': - status_addr = CSPRNG_ADDR_STATUS; - data_addr = CSPRNG_ADDR_RANDOM; - break; - case 'n': - num_words = strtoul(optarg, &endptr, 10); - switch (toupper(*endptr)) { - case '\0': - break; - case 'K': - num_words *= 1000; - break; - case 'M': - num_words *= 1000000; - break; - case 'G': - num_words *= 1000000000; - break; - default: - fprintf(stderr, "unsupported -n suffix %s\n", endptr); - return EXIT_FAILURE; - } - break; - case 'o': - output = fopen(optarg, "wb+"); - if (output == NULL) { - fprintf(stderr, "error opening output file %s: ", optarg); - perror(""); - return EXIT_FAILURE; - } - break; - default: - errout: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - if (optind < argc) { - fprintf(stderr, "%s: invalid argument%s --", - argv[0], argc - optind > 1 ? "s" : ""); - do { - fprintf(stderr, " %s", argv[optind]); - ++optind; - } while (optind < argc); - fprintf(stderr, "\n"); - goto errout; - } - - /* get the data */ - for (i = 0; i < num_words; ++i) { - if (extract(status_addr, data_addr, &data) != 0) - return EXIT_FAILURE; - if (fwrite(&data, sizeof(data), 1, output) != 1) { - perror("fwrite"); - fclose(output); - return EXIT_FAILURE; - } - } - - fclose(output); - return EXIT_SUCCESS; -} diff --git a/eim/sw/trng_tester_eim.c b/eim/sw/trng_tester_eim.c deleted file mode 100644 index def75ab..0000000 --- a/eim/sw/trng_tester_eim.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * trng_tester.c - * -------------- - * This program sends several commands to the TRNG subsystem - * in order to verify the avalanche_entropy, rosc_entropy, and csprng cores. - * - * Note: This version of the program talks to the FPGA over an EIM bus. - * - * - * Author: Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tc_eim.h" -#include "cryptech_memory_map.h" - -char *usage = "Usage: %s [-h] [-d] [-q] [-r] [-w] [-n #] tc...\n"; - -int debug = 0; -int quiet = 0; -int repeat = 0; -int num_words = 10; -int wait_stats = 0; - -/* ---------------- sanity test case ---------------- */ - -int TC0() -{ - uint8_t board_name0[4] = "PVT1"; - uint8_t board_name1[4] = " "; - uint8_t board_version[4] = "0.10"; - - uint8_t comm_name0[4] = "eim "; - uint8_t comm_name1[4] = " "; - uint8_t comm_version[4] = "0.10"; - - uint8_t t[4]; - - if (!quiet) - printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); - - /* write current time into dummy register, then try to read it back - * to make sure that we can actually write something into EIM - */ - (void)time((time_t *)t); - if (tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4) != 0) - return 1; - - if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || - tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || - tc_expected(BOARD_ADDR_VERSION, board_version, 4) || - tc_expected(BOARD_ADDR_DUMMY, (void *)t, 4)) - return 1; - - if (!quiet) - printf("TC0-2: Reading name and version words from communications core.\n"); - - return - tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || - tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || - tc_expected(COMM_ADDR_VERSION, comm_version, 4); -} - -/* ---------------- trng test cases ---------------- */ - -/* TC1: Read name and version from trng core. */ -int TC1(void) -{ - uint8_t name0[4] = "trng"; - uint8_t name1[4] = " "; - uint8_t version[4] = "0.01"; - - if (!quiet) - printf("TC1: Reading name and version words from trng core.\n"); - - return - tc_expected(TRNG_ADDR_NAME0, name0, 4) || - tc_expected(TRNG_ADDR_NAME1, name1, 4) || - tc_expected(TRNG_ADDR_VERSION, version, 4); -} - -/* XXX test cases for setting blinkenlights? */ -/* XXX set 'discard' control bit, see if we read the same value */ - -/* ---------------- avalanche_entropy test cases ---------------- */ - -/* TC2: Read name and version from avalanche_entropy core. */ -int TC2(void) -{ - uint8_t name0[4] = "extn"; - uint8_t name1[4] = "oise"; - uint8_t version[4] = "0.10"; - - if (!quiet) - printf("TC2: Reading name and version words from avalanche_entropy core.\n"); - - return - tc_expected(ENTROPY1_ADDR_NAME0, name0, 4) || - tc_expected(ENTROPY1_ADDR_NAME1, name1, 4) || - tc_expected(ENTROPY1_ADDR_VERSION, version, 4); -} - -/* XXX clear 'enable' control bit, see if we read the same value */ - -/* TC3: Read random data from avalanche_entropy. */ -int TC3(void) -{ - int i, n; - uint32_t entropy; - - if (!quiet) - printf("TC3: Read random data from avalanche_entropy.\n"); - - for (i = 0; i < num_words; ++i) { - /* check status */ - n = 0; - if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID, &n) != 0) - return 1; - /* read entropy data */ - if (tc_read(ENTROPY1_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) - return 1; - /* display entropy data */ - if (!debug) { - if (wait_stats) - printf("%08x %d\n", entropy, n); - else - printf("%08x\n", entropy); - } - } - - return 0; -} - -/* ---------------- rosc_entropy test cases ---------------- */ - -/* TC4: Read name and version from rosc_entropy core. */ -int TC4(void) -{ - uint8_t name0[4] = "rosc"; - uint8_t name1[4] = " ent"; - uint8_t version[4] = "0.10"; - - if (!quiet) - printf("TC4: Reading name and version words from rosc_entropy core.\n"); - - return - tc_expected(ENTROPY2_ADDR_NAME0, name0, 4) || - tc_expected(ENTROPY2_ADDR_NAME1, name1, 4) || - tc_expected(ENTROPY2_ADDR_VERSION, version, 4); -} - -/* XXX clear 'enable' control bit, see if we read the same value */ - -/* TC5: Read random data from rosc_entropy. */ -int TC5(void) -{ - int i, n; - uint32_t entropy; - - if (!quiet) - printf("TC5: Read random data from rosc_entropy.\n"); - - for (i = 0; i < num_words; ++i) { - /* check status */ - n = 0; - if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID, &n) != 0) - return 1; - /* read entropy data */ - if (tc_read(ENTROPY2_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) - return 1; - /* display entropy data */ - if (!debug) { - if (wait_stats) - printf("%08x %d\n", entropy, n); - else - printf("%08x\n", entropy); - } - } - - return 0; -} - -/* ---------------- trng_csprng test cases ---------------- */ - -/* TC6: Read name and version from trng_csprng core. */ -int TC6(void) -{ - /* XXX csprng core currently doesn't have name/version registers */ - return 0; -} - -/* XXX clear 'enable' control bit, see if we read the same value */ -/* XXX set 'seed' control bit, see if we read the same value */ - -/* TC7: Read random data from trng_csprng. */ -int TC7(void) -{ - int i, n; - uint32_t random; - - if (!quiet) - printf("TC7: Read random data from trng_csprng.\n"); - - for (i = 0; i < num_words; ++i) { - /* check status */ - n = 0; - if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID, &n) != 0) - return 1; - /* read random data */ - if (tc_read(CSPRNG_ADDR_RANDOM, (uint8_t *)&random, 4) != 0) - return 1; - /* display random data */ - if (!debug) { - if (wait_stats) - printf("%08x %d\n", random, n); - else - printf("%08x\n", random); - } - } - - return 0; -} - - -/* ---------------- main ---------------- */ - -/* signal handler for ctrl-c to end repeat testing */ -unsigned long iter = 0; -struct timeval tv_start, tv_end; -void sighandler(int unused) -{ - double tv_diff; - - gettimeofday(&tv_end, NULL); - tv_diff = (double)(tv_end.tv_sec - tv_start.tv_sec) + - (double)(tv_end.tv_usec - tv_start.tv_usec)/1000000; - printf("\n%lu iterations in %.3f seconds (%.3f iterations/sec)\n", - iter, tv_diff, (double)iter/tv_diff); - exit(EXIT_SUCCESS); -} - -int main(int argc, char *argv[]) -{ - typedef int (*tcfp)(void); - tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 }; - int i, j, opt; - - while ((opt = getopt(argc, argv, "h?dqrn:w")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'd': - debug = 1; - break; - case 'q': - quiet = 1; - break; - case 'r': - repeat = 1; - break; - case 'n': - num_words = atoi(optarg); - if (num_words <= 0) { - fprintf(stderr, "-n requires a positive integer argument\n"); - return EXIT_FAILURE; - } - break; - case 'w': - wait_stats = 1; - break; - default: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - - /* repeat one test until interrupted */ - if (repeat) { - tcfp tc; - if (optind != argc - 1) { - fprintf(stderr, "only one test case can be repeated\n"); - return EXIT_FAILURE; - } - j = atoi(argv[optind]); - if (j < 0 || j >= sizeof(all_tests)/sizeof(all_tests[0])) { - fprintf(stderr, "invalid test number %s\n", argv[optind]); - return EXIT_FAILURE; - } - tc = (all_tests[j]); - srand(time(NULL)); - signal(SIGINT, sighandler); - gettimeofday(&tv_start, NULL); - while (1) { - ++iter; - if ((iter & 0xffff) == 0) { - printf("."); - fflush(stdout); - } - if (tc() != 0) - sighandler(0); - } - return EXIT_SUCCESS; /*NOTREACHED*/ - } - - /* no args == run all tests */ - if (optind >= argc) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - return EXIT_SUCCESS; - } - - /* run one or more tests (by number) or groups of tests (by name) */ - for (i = optind; i < argc; ++i) { - if (strcmp(argv[i], "all") == 0) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (isdigit(argv[i][0]) && - (((j = atoi(argv[i])) >= 0) && - (j < sizeof(all_tests)/sizeof(all_tests[0])))) { - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else { - fprintf(stderr, "unknown test case %s\n", argv[i]); - return EXIT_FAILURE; - } - } - - return EXIT_SUCCESS; -} diff --git a/i2c/sw/Makefile b/i2c/sw/Makefile deleted file mode 100755 index 9869e04..0000000 --- a/i2c/sw/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -all: hash_tester_i2c trng_tester_i2c hash_i2c trng_extractor_i2c - -.c.o: - gcc -c -Wall -o $@ $< - -hash_tester_i2c: hash_tester_i2c.o tc_i2c.o - gcc -o $@ $^ - -hash_tester_i2c.o: hash_tester_i2c.c tc_i2c.h - -trng_tester_i2c: trng_tester_i2c.o tc_i2c.o - gcc -o $@ $^ - -trng_tester_i2c.o: trng_tester_i2c.c tc_i2c.h - -hash_i2c: hash_i2c.o tc_i2c.o - gcc -o $@ $^ - -hash_i2c.o: hash_i2c.c tc_i2c.h - -trng_extractor_i2c: trng_extractor_i2c.o tc_i2c.o - gcc -o $@ $^ - -trng_extractor_i2c.o: trng_extractor_i2c.c tc_i2c.h - -tc_i2c.o: tc_i2c.c tc_i2c.h - -clean: - rm -f *.o hash_tester_i2c trng_tester_i2c hash_i2c trng_extractor_i2c diff --git a/i2c/sw/cryptech_memory_map.h b/i2c/sw/cryptech_memory_map.h deleted file mode 100644 index 5cf7f42..0000000 --- a/i2c/sw/cryptech_memory_map.h +++ /dev/null @@ -1,217 +0,0 @@ -//====================================================================== -// -// cryptech_memory_map.h -// --------------------- -// The memory map for Cryptech cores. -// -// -// Authors: Joachim Strombergson, Paul Selkirk -// Copyright (c) 2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -// BASE_ADDR, SEGMENT_SIZE, and ADDR are defined in tc_[eim|i2c].h, -// which #includes this file. - -// default definitions from i2c, because defaults are good -#ifndef BASE_ADDR -#define BASE_ADDR 0 -#endif -#ifndef SEGMENT_SIZE -#define SEGMENT_SIZE 0x2000 -#endif -#ifndef ADDR -#define ADDR(x) (x) -#endif - -#ifndef bitsToBytes -#define bitsToBytes(x) (x / 8) -#endif - -// Segments. -#define SEGMENT_OFFSET_GLOBALS BASE_ADDR + (0 * SEGMENT_SIZE) -#define SEGMENT_OFFSET_HASHES BASE_ADDR + (1 * SEGMENT_SIZE) -#define SEGMENT_OFFSET_RNGS BASE_ADDR + (2 * SEGMENT_SIZE) -#define SEGMENT_OFFSET_CIPHERS BASE_ADDR + (3 * SEGMENT_SIZE) - - -// addresses and codes common to all cores -#define ADDR_NAME0 ADDR(0x00) -#define ADDR_NAME1 ADDR(0x01) -#define ADDR_VERSION ADDR(0x02) - - -//------------------------------------------------------------------ -// Board segment. -// Board-level registers and communication channel registers -//------------------------------------------------------------------ -#define BOARD_CORE_SIZE ADDR(0x100) - -#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0 * BOARD_CORE_SIZE) -#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 -#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 -#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION -#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + ADDR(0xFF) - -#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (1 * BOARD_CORE_SIZE) -#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 -#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 -#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION - - -//------------------------------------------------------------------ -// Hashes segment. -//------------------------------------------------------------------ -#define HASH_CORE_SIZE ADDR(0x100) - -// addresses and codes common to all hash cores */ -#define ADDR_CTRL ADDR(0x8) -#define CTRL_INIT_CMD 1 -#define CTRL_NEXT_CMD 2 -#define ADDR_STATUS ADDR(0x9) -#define STATUS_READY_BIT 1 -#define STATUS_VALID_BIT 2 -#define ADDR_BLOCK ADDR(0x10) -#define ADDR_DIGEST ADDR(0x20) // except SHA512 - -// addresses and codes for the specific hash cores. -#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0 * HASH_CORE_SIZE) -#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 -#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 -#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION -#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL -#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS -#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK -#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST -#define SHA1_BLOCK_LEN bitsToBytes(512) -#define SHA1_LENGTH_LEN bitsToBytes(64) -#define SHA1_DIGEST_LEN bitsToBytes(160) - -#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1 * HASH_CORE_SIZE) -#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 -#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 -#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION -#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL -#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS -#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK -#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST -#define SHA256_BLOCK_LEN bitsToBytes(512) -#define SHA256_LENGTH_LEN bitsToBytes(64) -#define SHA256_DIGEST_LEN bitsToBytes(256) - -#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2 * HASH_CORE_SIZE) -#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 -#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 -#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION -#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL -#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS -#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK -#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + ADDR(0x40) -#define SHA512_BLOCK_LEN bitsToBytes(1024) -#define SHA512_LENGTH_LEN bitsToBytes(128) -#define SHA512_224_DIGEST_LEN bitsToBytes(224) -#define SHA512_256_DIGEST_LEN bitsToBytes(256) -#define SHA384_DIGEST_LEN bitsToBytes(384) -#define SHA512_DIGEST_LEN bitsToBytes(512) -#define MODE_SHA_512_224 0 << 2 -#define MODE_SHA_512_256 1 << 2 -#define MODE_SHA_384 2 << 2 -#define MODE_SHA_512 3 << 2 - - -// ----------------------------------------------------------------- -// TRNG segment. -// ----------------------------------------------------------------- -#define TRNG_CORE_SIZE ADDR(0x100) - -// addresses and codes for the TRNG cores */ -#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0 * TRNG_CORE_SIZE) -#define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 -#define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 -#define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION -#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + ADDR(0x10) -#define TRNG_CTRL_DISCARD 1 -#define TRNG_CTRL_TEST_MODE 2 -#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + ADDR(0x11) -// no status bits defined (yet) -#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + ADDR(0x13) - -#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (5 * TRNG_CORE_SIZE) -#define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 -#define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 -#define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION -#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + ADDR(0x10) -#define ENTROPY1_CTRL_ENABLE 1 -#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + ADDR(0x11) -#define ENTROPY1_STATUS_VALID 1 -#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + ADDR(0x20) -#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + ADDR(0x30) - -#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (6 * TRNG_CORE_SIZE) -#define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 -#define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 -#define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION -#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + ADDR(0x10) -#define ENTROPY2_CTRL_ENABLE 1 -#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + ADDR(0x11) -#define ENTROPY2_STATUS_VALID 1 -#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + ADDR(0x18) -#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + ADDR(0x19) -#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + ADDR(0x20) -#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + ADDR(0x21) -#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + ADDR(0x22) - -#define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * TRNG_CORE_SIZE) -#define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 -#define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 -#define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION -#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + ADDR(0x10) -#define MIXER_CTRL_ENABLE 1 -#define MIXER_CTRL_RESTART 2 -#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + ADDR(0x11) -// no status bits defined (yet) -#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + ADDR(0x20) - -#define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * TRNG_CORE_SIZE) -#define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 -#define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 -#define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION -#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + ADDR(0x10) -#define CSPRNG_CTRL_ENABLE 1 -#define CSPRNG_CTRL_SEED 2 -#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + ADDR(0x11) -#define CSPRNG_STATUS_VALID 1 -#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + ADDR(0x20) -#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + ADDR(0x40) -#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + ADDR(0x41) -#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + ADDR(0x42) - -//====================================================================== -// EOF cryptech_memory_map.h -//====================================================================== diff --git a/i2c/sw/hash_i2c.c b/i2c/sw/hash_i2c.c deleted file mode 100644 index 3a9f0cf..0000000 --- a/i2c/sw/hash_i2c.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * hash.c - * ------ - * This program uses the coretest_hashes subsystem to produce a - * cryptographic hash of a file or input stream. It is a generalization - * of the hash_tester.c test program. - * - * Authors: Joachim Strömbergson, Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tc_i2c.h" -#include "cryptech_memory_map.h" - -char *usage = -"Usage: %s [-d] [-v] [-q] [algorithm [file]]\n" -"algorithms: sha-1, sha-256, sha-512/224, sha-512/256, sha-384, sha-512\n"; - -int debug = 0; -int quiet = 0; -int verbose = 0; - - -/* ---------------- algorithm lookup code ---------------- */ - -struct ctrl { - char *name; - off_t block_addr; - int block_len; - off_t digest_addr; - int digest_len; - int mode; -} ctrl[] = { - { "sha-1", SHA1_ADDR_BLOCK, SHA1_BLOCK_LEN, - SHA1_ADDR_DIGEST, SHA1_DIGEST_LEN, 0 }, - { "sha-256", SHA256_ADDR_BLOCK, SHA256_BLOCK_LEN, - SHA256_ADDR_DIGEST, SHA256_DIGEST_LEN, 0 }, - { "sha-512/224", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA512_224_DIGEST_LEN, MODE_SHA_512_224 }, - { "sha-512/256", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA512_256_DIGEST_LEN, MODE_SHA_512_256 }, - { "sha-384", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA384_DIGEST_LEN, MODE_SHA_384 }, - { "sha-512", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, - SHA512_ADDR_DIGEST, SHA512_DIGEST_LEN, MODE_SHA_512 }, - { NULL, 0, 0, 0 } -}; - -/* return the control structure for the given algorithm */ -struct ctrl *find_algo(char *algo) -{ - int i; - - for (i = 0; ctrl[i].name != NULL; ++i) - if (strcmp(ctrl[i].name, algo) == 0) - return &ctrl[i]; - - fprintf(stderr, "algorithm \"%s\" not found\n\n", algo); - fprintf(stderr, usage, "hash"); - return NULL; -} - -/* ---------------- hash ---------------- */ - -int transmit(off_t offset, uint8_t *block, int blen, int mode, int first) -{ - off_t base = offset & ~(0x1ff); - uint8_t ctrl_cmd[4] = { 0 }; - - if (tc_write(offset, block, blen) != 0) - return 1; - - ctrl_cmd[3] = (first ? CTRL_INIT_CMD : CTRL_NEXT_CMD) | mode; - - return - tc_write(base + ADDR_CTRL, ctrl_cmd, 4) || - tc_wait_ready(base + ADDR_STATUS); -} - -int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen, - uint8_t mode, long long tlen, int first) -{ - assert(flen < blen); - - block[flen++] = 0x80; - memset(block + flen, 0, blen - flen); - - if (blen - flen < ((blen == 64) ? 8 : 16)) { - if (transmit(offset, block, blen, mode, first) != 0) - return 1; - first = 0; - memset(block, 0, blen); - } - - /* properly the length is 128 bits for sha-512, but we can't - * actually count above 64 bits - */ - ((uint32_t *)block)[blen/4 - 2] = htonl((tlen >> 32) & 0xffff); - ((uint32_t *)block)[blen/4 - 1] = htonl(tlen & 0xffff); - - return transmit(offset, block, blen, mode, first); -} - -/* return number of digest bytes read */ -int hash(char *algo, char *file, uint8_t *digest) -{ - uint8_t block[SHA512_BLOCK_LEN]; - struct ctrl *ctrl; - int in_fd = 0; /* stdin */ - off_t baddr, daddr; - int blen, dlen, mode; - int nblk, nread, first; - int ret = -1; - struct timeval start, stop, difftime; - - ctrl = find_algo(algo); - if (ctrl == NULL) - return -1; - baddr = ctrl->block_addr; - blen = ctrl->block_len; - daddr = ctrl->digest_addr; - dlen = ctrl->digest_len; - mode = ctrl->mode; - - if (strcmp(file, "-") != 0) { - in_fd = open(file, O_RDONLY); - if (in_fd < 0) { - perror("open"); - return -1; - } - } - - if (verbose) { - if (gettimeofday(&start, NULL) < 0) { - perror("gettimeofday"); - goto out; - } - } - - for (nblk = 0, first = 1; ; ++nblk, first = 0) { - nread = read(in_fd, block, blen); - if (nread < 0) { - /* read error */ - perror("read"); - goto out; - } - else if (nread < blen) { - /* partial read = last block */ - if (pad_transmit(baddr, block, nread, blen, mode, - (nblk * blen + nread) * 8, first) != 0) - goto out; - break; - } - else { - /* full block read */ - if (transmit(baddr, block, blen, mode, first) != 0) - goto out; - } - } - - /* Strictly speaking we should query "valid" status before reading digest, - * but transmit() waits for "ready" status before returning, and the SHA - * cores always assert valid before ready. - */ - if (tc_read(daddr, digest, dlen) != 0) { - perror("i2c read failed"); - goto out; - } - - if (verbose) { - if (gettimeofday(&stop, NULL) < 0) { - perror("gettimeofday"); - goto out; - } - timersub(&stop, &start, &difftime); - printf("%d blocks written in %d.%03d sec (%.3f blocks/sec)\n", - nblk, (int)difftime.tv_sec, (int)difftime.tv_usec/1000, - (float)nblk / ((float)difftime.tv_sec + ((float)difftime.tv_usec)/1000000)); - } - - ret = dlen; -out: - if (in_fd != 0) - close(in_fd); - return ret; -} - -/* ---------------- main ---------------- */ - -int main(int argc, char *argv[]) -{ - int i, opt; - char *algo = "sha-1"; - char *file = "-"; - uint8_t digest[512/8]; - int dlen; - - while ((opt = getopt(argc, argv, "h?dvq")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'd': - debug = 1; - break; - case 'v': - verbose = 1; - break; - case 'q': - quiet = 1; - break; - default: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - - if (optind < argc) { - algo = argv[optind]; - ++optind; - } - else { - if (!quiet) - printf("defaulting to algorithm \"%s\"\n", algo); - } - - if (optind < argc) { - file = argv[optind]; - ++optind; - } - else { - if (!quiet) - printf("reading from stdin\n"); - } - - dlen = hash(algo, file, digest); - if (dlen < 0) - return EXIT_FAILURE; - - for (i = 0; i < dlen; ++i) { - printf("%02x", digest[i]); - if (i % 16 == 15) - printf("\n"); - else if (i % 4 == 3) - printf(" "); - } - if (dlen % 16 != 0) - printf("\n"); - - return EXIT_SUCCESS; -} diff --git a/i2c/sw/hash_tester_i2c.c b/i2c/sw/hash_tester_i2c.c deleted file mode 100644 index 41a117e..0000000 --- a/i2c/sw/hash_tester_i2c.c +++ /dev/null @@ -1,634 +0,0 @@ -/* - * hash_tester.c - * -------------- - * This program sends several commands to the coretest_hashes subsystem - * in order to verify the SHA-1, SHA-256 and SHA-512/x hash function - * cores. - * - * Note: This version of the program talks to the FPGA over an I2C bus. - * - * The single and dual block test cases are taken from the - * NIST KAT document: - * http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf - * - * - * Authors: Joachim Strömbergson, Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "tc_i2c.h" -#include "cryptech_memory_map.h" - -int debug = 0; -int quiet = 0; - - -/* SHA-1/SHA-256 One Block Message Sample - Input Message: "abc" */ -const uint8_t NIST_512_SINGLE[] = -{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; - -const uint8_t SHA1_SINGLE_DIGEST[] = -{ 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, - 0xba, 0x3e, 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, - 0x9c, 0xd0, 0xd8, 0x9d }; - -const uint8_t SHA256_SINGLE_DIGEST[] = -{ 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, - 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, - 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, - 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }; - -/* SHA-1/SHA-256 Two Block Message Sample - Input Message: "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" */ -const uint8_t NIST_512_DOUBLE0[] = -{ 0x61, 0x62, 0x63, 0x64, 0x62, 0x63, 0x64, 0x65, - 0x63, 0x64, 0x65, 0x66, 0x64, 0x65, 0x66, 0x67, - 0x65, 0x66, 0x67, 0x68, 0x66, 0x67, 0x68, 0x69, - 0x67, 0x68, 0x69, 0x6A, 0x68, 0x69, 0x6A, 0x6B, - 0x69, 0x6A, 0x6B, 0x6C, 0x6A, 0x6B, 0x6C, 0x6D, - 0x6B, 0x6C, 0x6D, 0x6E, 0x6C, 0x6D, 0x6E, 0x6F, - 0x6D, 0x6E, 0x6F, 0x70, 0x6E, 0x6F, 0x70, 0x71, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -const uint8_t NIST_512_DOUBLE1[] = -{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0 }; - -const uint8_t SHA1_DOUBLE_DIGEST[] = -{ 0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, - 0xBA, 0xAE, 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, - 0xE5, 0x46, 0x70, 0xF1 }; - -const uint8_t SHA256_DOUBLE_DIGEST[] = -{ 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, - 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, - 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, - 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }; - -/* SHA-512 One Block Message Sample - Input Message: "abc" */ -const uint8_t NIST_1024_SINGLE[] = -{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; - -const uint8_t SHA512_224_SINGLE_DIGEST[] = -{ 0x46, 0x34, 0x27, 0x0f, 0x70, 0x7b, 0x6a, 0x54, - 0xda, 0xae, 0x75, 0x30, 0x46, 0x08, 0x42, 0xe2, - 0x0e, 0x37, 0xed, 0x26, 0x5c, 0xee, 0xe9, 0xa4, - 0x3e, 0x89, 0x24, 0xaa }; -const uint8_t SHA512_256_SINGLE_DIGEST[] = -{ 0x53, 0x04, 0x8e, 0x26, 0x81, 0x94, 0x1e, 0xf9, - 0x9b, 0x2e, 0x29, 0xb7, 0x6b, 0x4c, 0x7d, 0xab, - 0xe4, 0xc2, 0xd0, 0xc6, 0x34, 0xfc, 0x6d, 0x46, - 0xe0, 0xe2, 0xf1, 0x31, 0x07, 0xe7, 0xaf, 0x23 }; -const uint8_t SHA384_SINGLE_DIGEST[] = -{ 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, - 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07, - 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, - 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, - 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23, - 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 }; -const uint8_t SHA512_SINGLE_DIGEST[] = -{ 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, - 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, - 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, - 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, - 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8, - 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, - 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, - 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f }; - -/* SHA-512 Two Block Message Sample - Input Message: "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" - "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" */ -const uint8_t NIST_1024_DOUBLE0[] = -{ 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, - 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, - 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, - 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, - 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, - 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, - 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, - 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, - 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, - 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, - 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, - 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -const uint8_t NIST_1024_DOUBLE1[] = -{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80 }; - -const uint8_t SHA512_224_DOUBLE_DIGEST[] = -{ 0x23, 0xfe, 0xc5, 0xbb, 0x94, 0xd6, 0x0b, 0x23, - 0x30, 0x81, 0x92, 0x64, 0x0b, 0x0c, 0x45, 0x33, - 0x35, 0xd6, 0x64, 0x73, 0x4f, 0xe4, 0x0e, 0x72, - 0x68, 0x67, 0x4a, 0xf9 }; -const uint8_t SHA512_256_DOUBLE_DIGEST[] = -{ 0x39, 0x28, 0xe1, 0x84, 0xfb, 0x86, 0x90, 0xf8, - 0x40, 0xda, 0x39, 0x88, 0x12, 0x1d, 0x31, 0xbe, - 0x65, 0xcb, 0x9d, 0x3e, 0xf8, 0x3e, 0xe6, 0x14, - 0x6f, 0xea, 0xc8, 0x61, 0xe1, 0x9b, 0x56, 0x3a }; -const uint8_t SHA384_DOUBLE_DIGEST[] = -{ 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8, - 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47, - 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2, - 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12, - 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9, - 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 }; -const uint8_t SHA512_DOUBLE_DIGEST[] = -{ 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda, - 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f, - 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1, - 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18, - 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4, - 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a, - 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54, - 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 }; - -/* ---------------- sanity test case ---------------- */ - -int TC0() -{ - uint8_t board_name0[4] = "PVT1"; - uint8_t board_name1[4] = " "; - uint8_t board_version[4] = "0.10"; - - uint8_t comm_name0[4] = "i2c "; - uint8_t comm_name1[4] = " "; - uint8_t comm_version[4] = "0.10"; - - uint8_t t[4]; - - if (!quiet) - printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); - - /* write current time into dummy register, then try to read it back - * to make sure that we can actually write something into EIM - */ - (void)time((time_t *)t); - if (tc_write(BOARD_ADDR_DUMMY, t, 4) != 0) - return 1; - - if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || - tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || - tc_expected(BOARD_ADDR_VERSION, board_version, 4) || - tc_expected(BOARD_ADDR_DUMMY, t, 4)) - return 1; - - if (!quiet) - printf("TC0-2: Reading name and version words from communications core.\n"); - - return - tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || - tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || - tc_expected(COMM_ADDR_VERSION, comm_version, 4); -} - -/* ---------------- SHA-1 test cases ---------------- */ - -/* TC1: Read name and version from SHA-1 core. */ -int TC1(void) -{ - uint8_t name0[4] = "sha1"; - uint8_t name1[4] = " "; - uint8_t version[4] = "0.50"; - - if (!quiet) - printf("TC1: Reading name and version words from SHA-1 core.\n"); - - return - tc_expected(SHA1_ADDR_NAME0, name0, 4) || - tc_expected(SHA1_ADDR_NAME1, name1, 4) || - tc_expected(SHA1_ADDR_VERSION, version, 4); -} - -/* TC2: SHA-1 Single block message test as specified by NIST. */ -int TC2(void) -{ - const uint8_t *block = NIST_512_SINGLE; - const uint8_t *expected = SHA1_SINGLE_DIGEST; - int ret; - - if (!quiet) - printf("TC2: Single block message test for SHA-1.\n"); - - /* Write block to SHA-1. */ - tc_write(SHA1_ADDR_BLOCK, block, SHA1_BLOCK_LEN); - /* Start initial block hashing, wait and check status. */ - tc_init(SHA1_ADDR_CTRL); - tc_wait_valid(SHA1_ADDR_STATUS); - /* Extract the digest. */ - ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); - return ret; -} - -/* TC3: SHA-1 Double block message test as specified by NIST. */ -int TC3(void) -{ - const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; - static const uint8_t block0_expected[] = - { 0xF4, 0x28, 0x68, 0x18, 0xC3, 0x7B, 0x27, 0xAE, - 0x04, 0x08, 0xF5, 0x81, 0x84, 0x67, 0x71, 0x48, - 0x4A, 0x56, 0x65, 0x72 }; - const uint8_t *expected = SHA1_DOUBLE_DIGEST; - int ret; - - if (!quiet) - printf("TC3: Double block message test for SHA-1.\n"); - - /* Write first block to SHA-1. */ - tc_write(SHA1_ADDR_BLOCK, block[0], SHA1_BLOCK_LEN); - /* Start initial block hashing, wait and check status. */ - tc_init(SHA1_ADDR_CTRL); - tc_wait_valid(SHA1_ADDR_STATUS); - /* Extract the first digest. */ - tc_expected(SHA1_ADDR_DIGEST, block0_expected, SHA1_DIGEST_LEN); - /* Write second block to SHA-1. */ - tc_write(SHA1_ADDR_BLOCK, block[1], SHA1_BLOCK_LEN); - /* Start next block hashing, wait and check status. */ - tc_next(SHA1_ADDR_CTRL); - tc_wait_valid(SHA1_ADDR_STATUS); - /* Extract the second digest. */ - ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); - return ret; -} - -/* ---------------- SHA-256 test cases ---------------- */ - -/* TC4: Read name and version from SHA-256 core. */ -int TC4(void) -{ - uint8_t name0[4] = "sha2"; - uint8_t name1[4] = "-256"; - uint8_t version[4] = "0.80"; - - if (!quiet) - printf("TC4: Reading name, type and version words from SHA-256 core.\n"); - - return - tc_expected(SHA256_ADDR_NAME0, name0, 4) || - tc_expected(SHA256_ADDR_NAME1, name1, 4) || - tc_expected(SHA256_ADDR_VERSION, version, 4); -} - -/* TC5: SHA-256 Single block message test as specified by NIST. */ -int TC5() -{ - const uint8_t *block = NIST_512_SINGLE; - const uint8_t *expected = SHA256_SINGLE_DIGEST; - - if (!quiet) - printf("TC5: Single block message test for SHA-256.\n"); - - return - /* Write block to SHA-256. */ - tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_init(SHA256_ADDR_CTRL) || - tc_wait_valid(SHA256_ADDR_STATUS) || - /* Extract the digest. */ - tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); -} - -/* TC6: SHA-256 Double block message test as specified by NIST. */ -int TC6() -{ - const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; - static const uint8_t block0_expected[] = - { 0x85, 0xE6, 0x55, 0xD6, 0x41, 0x7A, 0x17, 0x95, - 0x33, 0x63, 0x37, 0x6A, 0x62, 0x4C, 0xDE, 0x5C, - 0x76, 0xE0, 0x95, 0x89, 0xCA, 0xC5, 0xF8, 0x11, - 0xCC, 0x4B, 0x32, 0xC1, 0xF2, 0x0E, 0x53, 0x3A }; - const uint8_t *expected = SHA256_DOUBLE_DIGEST; - - if (!quiet) - printf("TC6: Double block message test for SHA-256.\n"); - - return - /* Write first block to SHA-256. */ - tc_write(SHA256_ADDR_BLOCK, block[0], SHA256_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_init(SHA256_ADDR_CTRL) || - tc_wait_valid(SHA256_ADDR_STATUS) || - /* Extract the first digest. */ - tc_expected(SHA256_ADDR_DIGEST, block0_expected, SHA256_DIGEST_LEN) || - /* Write second block to SHA-256. */ - tc_write(SHA256_ADDR_BLOCK, block[1], SHA256_BLOCK_LEN) || - /* Start next block hashing, wait and check status. */ - tc_next(SHA256_ADDR_CTRL) || - tc_wait_valid(SHA256_ADDR_STATUS) || - /* Extract the second digest. */ - tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); -} - -/* TC7: SHA-256 Huge message test. */ -int TC7() -{ - static const uint8_t block[] = - { 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, - 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, - 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, - 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, - 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f }; - - /* final digest after 1000 iterations */ - static const uint8_t expected[] = - { 0x76, 0x38, 0xf3, 0xbc, 0x50, 0x0d, 0xd1, 0xa6, - 0x58, 0x6d, 0xd4, 0xd0, 0x1a, 0x15, 0x51, 0xaf, - 0xd8, 0x21, 0xd2, 0x35, 0x2f, 0x91, 0x9e, 0x28, - 0xd5, 0x84, 0x2f, 0xab, 0x03, 0xa4, 0x0f, 0x2a }; - - int i, n = 1000; - - if (!quiet) - printf("TC7: Message with %d blocks test for SHA-256.\n", n); - - /* Write block data to SHA-256. */ - if (tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN)) - return 1; - - /* Start initial block hashing, wait and check status. */ - if (tc_init(SHA256_ADDR_CTRL) || - tc_wait_ready(SHA256_ADDR_STATUS)) - return 1; - - /* First block done. Do the rest. */ - for (i = 1; i < n; ++i) { - /* Start next block hashing, wait and check status. */ - if (tc_next(SHA256_ADDR_CTRL) || - tc_wait_ready(SHA256_ADDR_STATUS)) - return 1; - } - - /* XXX valid is probably set at the same time as ready */ - if (tc_wait_valid(SHA256_ADDR_STATUS)) - return 1; - /* Extract the final digest. */ - return tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); -} - -/* ---------------- SHA-512 test cases ---------------- */ - -/* TC8: Read name and version from SHA-512 core. */ -int TC8() -{ - uint8_t name0[4] = "sha2"; - uint8_t name1[4] = "-512"; - uint8_t version[4] = "0.80"; - - if (!quiet) - printf("TC8: Reading name, type and version words from SHA-512 core.\n"); - - return - tc_expected(SHA512_ADDR_NAME0, name0, 4) || - tc_expected(SHA512_ADDR_NAME1, name1, 4) || - tc_expected(SHA512_ADDR_VERSION, version, 4); -} - -/* TC9: SHA-512 Single block message test as specified by NIST. - We do this for all modes. */ -int tc9(int mode, const uint8_t *expected, int digest_len) -{ - const uint8_t *block = NIST_1024_SINGLE; - uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; - - return - /* Write block to SHA-512. */ - tc_write(SHA512_ADDR_BLOCK, block, SHA512_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_write(SHA512_ADDR_CTRL, init, 4) || - tc_wait_valid(SHA512_ADDR_STATUS) || - /* Extract the digest. */ - tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); -} - -int TC9() -{ - if (!quiet) - printf("TC9-1: Single block message test for SHA-512/224.\n"); - if (tc9(MODE_SHA_512_224, SHA512_224_SINGLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC9-2: Single block message test for SHA-512/256.\n"); - if (tc9(MODE_SHA_512_256, SHA512_256_SINGLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC9-3: Single block message test for SHA-384.\n"); - if (tc9(MODE_SHA_384, SHA384_SINGLE_DIGEST, SHA384_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC9-4: Single block message test for SHA-512.\n"); - if (tc9(MODE_SHA_512, SHA512_SINGLE_DIGEST, SHA512_DIGEST_LEN) != 0) - return 1; - - return 0; -} - -/* TC10: SHA-512 Double block message test as specified by NIST. - We do this for all modes. */ -int tc10(int mode, const uint8_t *expected, int digest_len) -{ - const uint8_t *block[2] = { NIST_1024_DOUBLE0, NIST_1024_DOUBLE1 }; - uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; - uint8_t next[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode }; - - return - /* Write first block to SHA-512. */ - tc_write(SHA512_ADDR_BLOCK, block[0], SHA512_BLOCK_LEN) || - /* Start initial block hashing, wait and check status. */ - tc_write(SHA512_ADDR_CTRL, init, 4) || - tc_wait_ready(SHA512_ADDR_STATUS) || - /* Write second block to SHA-512. */ - tc_write(SHA512_ADDR_BLOCK, block[1], SHA512_BLOCK_LEN) || - /* Start next block hashing, wait and check status. */ - tc_write(SHA512_ADDR_CTRL, next, 4) || - tc_wait_valid(SHA512_ADDR_STATUS) || - /* Extract the digest. */ - tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); -} - -int TC10() -{ - if (!quiet) - printf("TC10-1: Double block message test for SHA-512/224.\n"); - if (tc10(MODE_SHA_512_224, SHA512_224_DOUBLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC10-2: Double block message test for SHA-512/256.\n"); - if (tc10(MODE_SHA_512_256, SHA512_256_DOUBLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC10-3: Double block message test for SHA-384.\n"); - if (tc10(MODE_SHA_384, SHA384_DOUBLE_DIGEST, SHA384_DIGEST_LEN) != 0) - return 1; - - if (!quiet) - printf("TC10-4: Double block message test for SHA-512.\n"); - if (tc10(MODE_SHA_512, SHA512_DOUBLE_DIGEST, SHA512_DIGEST_LEN) != 0) - return 1; - - return 0; -} - -/* ---------------- main ---------------- */ - -int main(int argc, char *argv[]) -{ - typedef int (*tcfp)(void); - tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7, TC8, TC9, TC10 }; - tcfp sha1_tests[] = { TC1, TC2, TC3 }; - tcfp sha256_tests[] = { TC4, TC5, TC6, TC7 }; - tcfp sha512_tests[] = { TC8, TC9, TC10 }; - - char *usage = "Usage: %s [-h] [-d] [-q] tc...\n"; - int i, j, opt; - - while ((opt = getopt(argc, argv, "h?dq")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'd': - debug = 1; - break; - case 'q': - quiet = 1; - break; - default: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - - /* no args == run all tests */ - if (optind >= argc) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - return EXIT_SUCCESS; - } - - /* run one or more tests (by number) or groups of tests (by name) */ - for (i = optind; i < argc; ++i) { - if (strcmp(argv[i], "all") == 0) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (strcmp(argv[i], "sha1") == 0) { - for (j = 0; j < sizeof(sha1_tests)/sizeof(sha1_tests[0]); ++j) - if (sha1_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (strcmp(argv[i], "sha256") == 0) { - for (j = 0; j < sizeof(sha256_tests)/sizeof(sha256_tests[0]); ++j) - if (sha256_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (strcmp(argv[i], "sha512") == 0) { - for (j = 0; j < sizeof(sha512_tests)/sizeof(sha512_tests[0]); ++j) - if (sha512_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (isdigit(argv[i][0]) && - (((j = atoi(argv[i])) >= 0) && - (j < sizeof(all_tests)/sizeof(all_tests[0])))) { - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else { - fprintf(stderr, "unknown test case %s\n", argv[i]); - return EXIT_FAILURE; - } - } - - return EXIT_SUCCESS; -} diff --git a/i2c/sw/tc_i2c.c b/i2c/sw/tc_i2c.c deleted file mode 100644 index 613d1c6..0000000 --- a/i2c/sw/tc_i2c.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * tc_i2c.c - * -------- - * This module contains common code to talk to the FPGA over the I2C bus. - * - * Author: Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include - -#include "tc_i2c.h" - -extern int debug; - -/* ---------------- I2C low-level code ---------------- */ - -static int i2cfd = -1; - -static void dump(char *label, const uint8_t *buf, size_t len) -{ - if (debug) { - int i; - printf("%s [", label); - for (i = 0; i < len; ++i) - printf(" %02x", buf[i]); - printf(" ]\n"); - } -} - -static void i2c_close(void) -{ - close(i2cfd); -} - -static int i2c_open(void) -{ - if (i2cfd >= 0) - return 0; - - i2cfd = open(I2C_dev, O_RDWR); - if (i2cfd < 0) { - fprintf(stderr, "Unable to open %s: ", I2C_dev); - perror(""); - i2cfd = 0; - return 1; - } - - if (ioctl(i2cfd, I2C_SLAVE, I2C_addr) < 0) { - fprintf(stderr, "Unable to set I2C slave device 0x%02x: ", I2C_addr); - perror(""); - return 1; - } - - if (atexit(i2c_close) != 0) { - fprintf(stderr, "Unable to set I2C atexit handler."); - return 1; - } - - return 0; -} - -static int i2c_write(const uint8_t *buf, size_t len) -{ - if (i2c_open() != 0) - return 1; - - dump("write ", buf, len); - - if (write(i2cfd, buf, len) != len) { - perror("i2c write failed"); - return 1; - } - - return 0; -} - -static int i2c_read(uint8_t *b) -{ - if (i2c_open() != 0) - return 1; - - /* read() on the i2c device only returns one byte at a time, - * and tc_get_resp() needs to parse the response one byte at a time - */ - if (read(i2cfd, b, 1) != 1) { - perror("i2c read failed"); - return 1; - } - - return 0; -} - -/* ---------------- test-case low-level code ---------------- */ - -/* coretest command codes */ -#define SOC 0x55 -#define EOC 0xaa -#define READ_CMD 0x10 -#define WRITE_CMD 0x11 -#define RESET_CMD 0x01 - -/* coretest response codes */ -#define SOR 0xaa -#define EOR 0x55 -#define READ_OK 0x7f -#define WRITE_OK 0x7e -#define RESET_OK 0x7d -#define UNKNOWN 0xfe -#define ERROR 0xfd - -static int tc_send_write_cmd(off_t offset, const uint8_t *data) -{ - uint8_t buf[9] = { SOC, WRITE_CMD, (offset >> 8) & 0xff, offset & 0xff, - data[0], data[1], data[2], data[3], EOC }; - - return i2c_write(buf, sizeof(buf)); -} - -static int tc_send_read_cmd(off_t offset) -{ - uint8_t buf[5] = { SOC, READ_CMD, (offset >> 8) & 0xff, offset & 0xff, EOC }; - - return i2c_write(buf, sizeof(buf)); -} - -static int tc_get_resp(uint8_t *buf, size_t len) -{ - int i; - - for (i = 0; i < len; ++i) { - if (i2c_read(&buf[i]) != 0) - return 1; - if ((i == 0) && (buf[i] != SOR)) { - /* we've gotten out of sync, and there's probably nothing we can do */ - fprintf(stderr, "response byte 0: expected 0x%02x (SOR), got 0x%02x\n", - SOR, buf[0]); - return 1; - } - else if (i == 1) { /* response code */ - switch (buf[i]) { - case READ_OK: - len = 9; - break; - case WRITE_OK: - len = 5; - break; - case RESET_OK: - len = 3; - break; - case ERROR: - case UNKNOWN: - len = 4; - break; - default: - /* we've gotten out of sync, and there's probably nothing we can do */ - fprintf(stderr, "unknown response code 0x%02x\n", buf[i]); - return 1; - } - } - } - - dump("read ", buf, len); - - return 0; -} - -static int tc_compare(uint8_t *buf, const uint8_t *expected, size_t len) -{ - int i; - - /* start at byte 1 because SOR has already been tested */ - for (i = 1; i < len; ++i) { - if (buf[i] != expected[i]) { - fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", - i, expected[i], buf[i]); - return 1; - } - } - - return 0; -} - -static int tc_get_write_resp(off_t offset) -{ - uint8_t buf[5]; - uint8_t expected[5] = { SOR, WRITE_OK, (offset >> 8) & 0xff, offset & 0xff, EOR }; - - return - tc_get_resp(buf, sizeof(buf)) || - tc_compare(buf, expected, sizeof(expected)); -} - -static int tc_get_read_resp(off_t offset, uint8_t *data) -{ - uint8_t buf[9]; - uint8_t expected[4] = { SOR, READ_OK, (offset >> 8) & 0xff, offset & 0xff }; - - if ((tc_get_resp(buf, sizeof(buf)) != 0) || - (tc_compare(buf, expected, 4) != 0) || buf[8] != EOR) - return 1; - - data[0] = buf[4]; - data[1] = buf[5]; - data[2] = buf[6]; - data[3] = buf[7]; - - return 0; -} - -static int tc_get_read_resp_expected(off_t offset, const uint8_t *data) -{ - uint8_t buf[9]; - uint8_t expected[9] = { SOR, READ_OK, (offset >> 8) & 0xff, offset & 0xff, - data[0], data[1], data[2], data[3], EOR }; - - dump("expect", expected, 9); - - return (tc_get_resp(buf, sizeof(buf)) || - tc_compare(buf, expected, sizeof(buf))); -} - -int tc_write(off_t offset, const uint8_t *buf, size_t len) -{ - for (; len > 0; offset++, buf += 4, len -= 4) { - if (tc_send_write_cmd(offset, buf) || - tc_get_write_resp(offset)) - return 1; - } - - return 0; -} - -int tc_read(off_t offset, uint8_t *buf, size_t len) -{ - for (; len > 0; offset++, buf += 4, len -= 4) { - if (tc_send_read_cmd(offset) || - tc_get_read_resp(offset, buf)) - return 1; - } - - return 0; -} - -int tc_expected(off_t offset, const uint8_t *buf, size_t len) -{ - for (; len > 0; offset++, buf += 4, len -= 4) { - if (tc_send_read_cmd(offset) || - tc_get_read_resp_expected(offset, buf)) - return 1; - } - - return 0; -} - -int tc_init(off_t offset) -{ - uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD }; - - return tc_write(offset, buf, 4); -} - -int tc_next(off_t offset) -{ - uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD }; - - return tc_write(offset, buf, 4); -} - -int tc_wait(off_t offset, uint8_t status, int *count) -{ - uint8_t buf[4]; - int i; - - for (i = 1; ; ++i) { - if (count && (*count > 0) && (i >= *count)) { - fprintf(stderr, "tc_wait timed out\n"); - return 1; - } - if (tc_read(offset, buf, 4) != 0) - return -1; - if (buf[3] & status) { - if (count) - *count = i; - return 0; - } - } -} - -int tc_wait_ready(off_t offset) -{ - int limit = 10; - return tc_wait(offset, STATUS_READY_BIT, &limit); -} - -int tc_wait_valid(off_t offset) -{ - int limit = 10; - return tc_wait(offset, STATUS_VALID_BIT, &limit); -} diff --git a/i2c/sw/tc_i2c.h b/i2c/sw/tc_i2c.h deleted file mode 100644 index b1afae1..0000000 --- a/i2c/sw/tc_i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * tc_i2c.h - * -------- - * This module contains common code to talk to the FPGA over the I2C bus. - * - * Author: Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* cryptech memory map */ -#define BASE_ADDR 0 -#define SEGMENT_SIZE 0x2000 -#define ADDR(x) (x) -#include "cryptech_memory_map.h" - -/* I2C configuration */ -#define I2C_dev "/dev/i2c-2" -#define I2C_addr 0x0f -#define I2C_SLAVE 0x0703 - -/* test case public functions */ -int tc_write(off_t offset, const uint8_t *data, size_t len); -int tc_read(off_t offset, uint8_t *data, size_t len); -int tc_expected(off_t offset, const uint8_t *data, size_t len); -int tc_init(off_t offset); -int tc_next(off_t offset); -int tc_wait(off_t offset, uint8_t status, int *count); -int tc_wait_ready(off_t offset); -int tc_wait_valid(off_t offset); diff --git a/i2c/sw/trng_extractor_i2c.c b/i2c/sw/trng_extractor_i2c.c deleted file mode 100644 index 7b3c2ef..0000000 --- a/i2c/sw/trng_extractor_i2c.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * trng_extractor.c - * ---------------- - * This program extracts raw data from the avalanche_entropy, rosc_entropy, - * and csprng cores. - * - * Author: Paul Selkirk - * Copyright (c) 2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "tc_i2c.h" -#include "cryptech_memory_map.h" - -char *usage = -"%s [-a|r|c] [-n #] [-o file]\n\ -\n\ --a avalanche entropy\n\ --r rosc entropy\n\ --c csprng (default data source)\n\ --n number of 4-byte samples (scale with K, M, or G suffix)\n\ --o output file (defaults to stdout)\n\ -"; - -int debug = 0; /* for dump() */ - -/* extract one data sample */ -static int extract(off_t status_addr, off_t data_addr, uint32_t *data) -{ -/* In theory, we should wait for "valid" before reading random - * data, but as long as this is running over I2C we're going to be so - * slow that there's no point, and checking would just make us slower. - */ -#define WAIT_FOR_TRNG_VALID 0 - -#if WAIT_FOR_TRNG_VALID - if (tc_wait(status_addr, ENTROPY1_STATUS_VALID, NULL) != 0) { - fprintf(stderr, "tc_wait failed\n"); - return 1; - } -#endif - - if (tc_read(data_addr, (uint8_t *)data, 4) != 0) { - fprintf(stderr, "tc_read failed\n"); - return 1; - } - - return 0; -} - -/* main */ -int main(int argc, char *argv[]) -{ - int i, opt; - unsigned long num_words = 1; - char *endptr; - off_t status_addr = CSPRNG_ADDR_STATUS; - off_t data_addr = CSPRNG_ADDR_RANDOM; - FILE *output = stdout; - uint32_t data; - - /* parse command line */ - while ((opt = getopt(argc, argv, "h?arcn:o:")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'a': - status_addr = ENTROPY1_ADDR_STATUS; - data_addr = ENTROPY1_ADDR_ENTROPY; - break; - case 'r': - status_addr = ENTROPY2_ADDR_STATUS; - data_addr = ENTROPY2_ADDR_ENTROPY; - break; - case 'c': - status_addr = CSPRNG_ADDR_STATUS; - data_addr = CSPRNG_ADDR_RANDOM; - break; - case 'n': - num_words = strtoul(optarg, &endptr, 10); - switch (toupper(*endptr)) { - case '\0': - break; - case 'K': - num_words *= 1000; - break; - case 'M': - num_words *= 1000000; - break; - case 'G': - num_words *= 1000000000; - break; - default: - fprintf(stderr, "unsupported -n suffix %s\n", endptr); - return EXIT_FAILURE; - } - break; - case 'o': - output = fopen(optarg, "wb+"); - if (output == NULL) { - fprintf(stderr, "error opening output file %s: ", optarg); - perror(""); - return EXIT_FAILURE; - } - break; - default: - errout: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - if (optind < argc) { - fprintf(stderr, "%s: invalid argument%s --", - argv[0], argc - optind > 1 ? "s" : ""); - do { - fprintf(stderr, " %s", argv[optind]); - ++optind; - } while (optind < argc); - fprintf(stderr, "\n"); - goto errout; - } - - /* get the data */ - for (i = 0; i < num_words; ++i) { - if (extract(status_addr, data_addr, &data) != 0) - return EXIT_FAILURE; - if (fwrite(&data, sizeof(data), 1, output) != 1) { - perror("fwrite"); - fclose(output); - return EXIT_FAILURE; - } - } - - fclose(output); - return EXIT_SUCCESS; -} diff --git a/i2c/sw/trng_tester_i2c.c b/i2c/sw/trng_tester_i2c.c deleted file mode 100644 index 92b2c94..0000000 --- a/i2c/sw/trng_tester_i2c.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * trng_tester.c - * -------------- - * This program sends several commands to the TRNG subsystem - * in order to verify the avalanche_entropy, rosc_entropy, and csprng cores. - * - * Note: This version of the program talks to the FPGA over an I2C bus. - * - * - * Author: Paul Selkirk - * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of the NORDUnet nor the names of its contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "tc_i2c.h" -#include "cryptech_memory_map.h" - -char *usage = "Usage: %s [-h] [-d] [-q] [-w] [-n #] tc...\n"; - -int debug = 0; -int quiet = 0; -int num_words = 10; -int wait_stats = 0; - -/* ---------------- sanity test case ---------------- */ - -int TC0() -{ - uint8_t board_name0[4] = "PVT1"; - uint8_t board_name1[4] = " "; - uint8_t board_version[4] = "0.10"; - - uint8_t comm_name0[4] = "i2c "; - uint8_t comm_name1[4] = " "; - uint8_t comm_version[4] = "0.10"; - - uint8_t t[4]; - - if (!quiet) - printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); - - /* write current time into dummy register, then try to read it back - * to make sure that we can actually write something into EIM - */ - (void)time((time_t *)t); - if (tc_write(BOARD_ADDR_DUMMY, t, 4) != 0) - return 1; - - if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || - tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || - tc_expected(BOARD_ADDR_VERSION, board_version, 4) || - tc_expected(BOARD_ADDR_DUMMY, t, 4)) - return 1; - - if (!quiet) - printf("TC0-2: Reading name and version words from communications core.\n"); - - return - tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || - tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || - tc_expected(COMM_ADDR_VERSION, comm_version, 4); -} - -/* ---------------- trng test cases ---------------- */ - -/* TC1: Read name and version from trng core. */ -int TC1(void) -{ - uint8_t name0[4] = "trng"; - uint8_t name1[4] = " "; - uint8_t version[4] = "0.01"; - - if (!quiet) - printf("TC1: Reading name and version words from trng core.\n"); - - return - tc_expected(TRNG_ADDR_NAME0, name0, 4) || - tc_expected(TRNG_ADDR_NAME1, name1, 4) || - tc_expected(TRNG_ADDR_VERSION, version, 4); -} - -/* XXX test cases for setting blinkenlights? */ -/* XXX set 'discard' control bit, see if we read the same value */ - -/* ---------------- avalanche_entropy test cases ---------------- */ - -/* TC2: Read name and version from avalanche_entropy core. */ -int TC2(void) -{ - uint8_t name0[4] = "extn"; - uint8_t name1[4] = "oise"; - uint8_t version[4] = "0.10"; - - if (!quiet) - printf("TC2: Reading name and version words from avalanche_entropy core.\n"); - - return - tc_expected(ENTROPY1_ADDR_NAME0, name0, 4) || - tc_expected(ENTROPY1_ADDR_NAME1, name1, 4) || - tc_expected(ENTROPY1_ADDR_VERSION, version, 4); -} - -/* XXX clear 'enable' control bit, see if we read the same value */ - -/* TC3: Read random data from avalanche_entropy. */ -int TC3(void) -{ - int i, n; - uint32_t entropy; - - if (!quiet) - printf("TC3: Read random data from avalanche_entropy.\n"); - - for (i = 0; i < num_words; ++i) { - /* check status */ - n = 10; - if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID, &n) != 0) - return 1; - /* read entropy data */ - if (tc_read(ENTROPY1_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) - return 1; - /* display entropy data */ - if (!debug) { - if (wait_stats) - printf("%08x %d\n", entropy, n); - else - printf("%08x\n", entropy); - } - } - - return 0; -} - -/* ---------------- rosc_entropy test cases ---------------- */ - -/* TC4: Read name and version from rosc_entropy core. */ -int TC4(void) -{ - uint8_t name0[4] = "rosc"; - uint8_t name1[4] = " ent"; - uint8_t version[4] = "0.10"; - - if (!quiet) - printf("TC4: Reading name and version words from rosc_entropy core.\n"); - - return - tc_expected(ENTROPY2_ADDR_NAME0, name0, 4) || - tc_expected(ENTROPY2_ADDR_NAME1, name1, 4) || - tc_expected(ENTROPY2_ADDR_VERSION, version, 4); -} - -/* XXX clear 'enable' control bit, see if we read the same value */ - -/* TC5: Read random data from rosc_entropy. */ -int TC5(void) -{ - int i, n; - uint32_t entropy; - - if (!quiet) - printf("TC5: Read random data from rosc_entropy.\n"); - - for (i = 0; i < num_words; ++i) { - /* check status */ - n = 10; - if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID, &n) != 0) - return 1; - /* read entropy data */ - if (tc_read(ENTROPY2_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) - return 1; - /* display entropy data */ - if (!debug) { - if (wait_stats) - printf("%08x %d\n", entropy, n); - else - printf("%08x\n", entropy); - } - } - - return 0; -} - -/* ---------------- trng_csprng test cases ---------------- */ - -/* TC6: Read name and version from trng_csprng core. */ -int TC6(void) -{ - /* XXX csprng core currently doesn't have name/version registers */ - return 0; -} - -/* XXX clear 'enable' control bit, see if we read the same value */ -/* XXX set 'seed' control bit, see if we read the same value */ - -/* TC7: Read random data from trng_csprng. */ -int TC7(void) -{ - int i, n; - uint32_t random; - - if (!quiet) - printf("TC7: Read random data from trng_csprng.\n"); - - for (i = 0; i < num_words; ++i) { - /* check status */ - n = 10; - if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID, &n) != 0) - return 1; - /* read random data */ - if (tc_read(CSPRNG_ADDR_RANDOM, (uint8_t *)&random, 4) != 0) - return 1; - /* display random data */ - if (!debug) { - if (wait_stats) - printf("%08x %d\n", random, n); - else - printf("%08x\n", random); - } - } - - return 0; -} - -/* ---------------- main ---------------- */ - -int main(int argc, char *argv[]) -{ - typedef int (*tcfp)(void); - tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 }; - int i, j, opt; - - while ((opt = getopt(argc, argv, "h?dqn:w")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return EXIT_SUCCESS; - case 'd': - debug = 1; - break; - case 'q': - quiet = 1; - break; - case 'n': - num_words = atoi(optarg); - if (num_words <= 0) { - fprintf(stderr, "-n requires a positive integer argument\n"); - return EXIT_FAILURE; - } - break; - case 'w': - wait_stats = 1; - break; - default: - fprintf(stderr, usage, argv[0]); - return EXIT_FAILURE; - } - } - - /* no args == run all tests */ - if (optind >= argc) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - return EXIT_SUCCESS; - } - - /* run one or more tests (by number) or groups of tests (by name) */ - for (i = optind; i < argc; ++i) { - if (strcmp(argv[i], "all") == 0) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else if (isdigit(argv[i][0]) && - (((j = atoi(argv[i])) >= 0) && - (j < sizeof(all_tests)/sizeof(all_tests[0])))) { - if (all_tests[j]() != 0) - return EXIT_FAILURE; - } - else { - fprintf(stderr, "unknown test case %s\n", argv[i]); - return EXIT_FAILURE; - } - } - - return EXIT_SUCCESS; -} diff --git a/sw/Makefile b/sw/Makefile new file mode 100755 index 0000000..93976d7 --- /dev/null +++ b/sw/Makefile @@ -0,0 +1,44 @@ +CC = gcc +CFLAGS = -Wall + +LIB = libcryptech.a +BIN = hash hash_tester trng_extractor trng_tester +INC = cryptech.h + +PREFIX = /usr/local +LIB_DIR = $(PREFIX)/lib +BIN_DIR = $(PREFIX)/bin +INC_DIR = $(PREFIX)/include + +all: $(LIB) $(BIN) + +%.o: %.c $(INC) + $(CC) $(CFLAGS) -c -o $@ $< + +libcryptech.a: tc_eim.o novena-eim.o + ar rcs $@ $^ + +hash_tester: hash_tester.o $(LIB) + $(CC) -o $@ $^ + +trng_tester: trng_tester.o $(LIB) + $(CC) -o $@ $^ + +hash: hash.o $(LIB) + $(CC) -o $@ $^ + +trng_extractor: trng_extractor.o $(LIB) + $(CC) -o $@ $^ + +install: $(LIB) $(BIN) $(INC) + install $(LIB) $(LIB_DIR) + install $(BIN) $(BIN_DIR) + install $(INC) $(INC_DIR) + +uninstall: + rm -f $(LIB_DIR)/$(LIB) + rm -f $(foreach bin,$(BIN),$(BIN_DIR)/$(bin)) + rm -f $(INC_DIR)/$(INC) + +clean: + rm -f *.o $(LIB) $(BIN) diff --git a/sw/Makefile.i2c b/sw/Makefile.i2c new file mode 100755 index 0000000..fa136a4 --- /dev/null +++ b/sw/Makefile.i2c @@ -0,0 +1,44 @@ +CC = gcc +CFLAGS = -Wall + +LIB = libcryptech_i2c.a +BIN = hash_i2c hash_tester_i2c trng_extractor_i2c trng_tester_i2c +INC = cryptech.h + +PREFIX = /usr/local +LIB_DIR = $(PREFIX)/lib +BIN_DIR = $(PREFIX)/bin +INC_DIR = $(PREFIX)/include + +all: $(LIB) $(BIN) + +%.o: %.c $(INC) + $(CC) $(CFLAGS) -c -o $@ $< + +libcryptech_i2c.a: tc_i2c.o + ar rcs $@ $^ + +hash_tester_i2c: hash_tester.o $(LIB) + $(CC) -o $@ $^ + +trng_tester_i2c: trng_tester.o $(LIB) + $(CC) -o $@ $^ + +hash_i2c: hash.o $(LIB) + $(CC) -o $@ $^ + +trng_extractor_i2c: trng_extractor.o $(LIB) + $(CC) -o $@ $^ + +install: $(LIB) $(BIN) $(INC) + install $(LIB) $(LIB_DIR) + install $(BIN) $(BIN_DIR) + install $(INC) $(INC_DIR) + +uninstall: + rm -f $(LIB_DIR)/$(LIB) + rm -f $(foreach bin,$(BIN),$(BIN_DIR)/$(bin)) + rm -f $(INC_DIR)/$(INC) + +clean: + rm -f *.o $(LIB) $(BIN) diff --git a/sw/cryptech.h b/sw/cryptech.h new file mode 100644 index 0000000..509c4e9 --- /dev/null +++ b/sw/cryptech.h @@ -0,0 +1,231 @@ +//====================================================================== +// +// cryptech.h +// ---------- +// Memory map and access functions for Cryptech cores. +// +// +// Authors: Joachim Strombergson, Paul Selkirk +// Copyright (c) 2015, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + + +// Segments. +#define SEGMENT_SIZE 0x2000 +#define SEGMENT_OFFSET_GLOBALS 0 * SEGMENT_SIZE +#define SEGMENT_OFFSET_HASHES 1 * SEGMENT_SIZE +#define SEGMENT_OFFSET_RNGS 2 * SEGMENT_SIZE +#define SEGMENT_OFFSET_CIPHERS 3 * SEGMENT_SIZE + + +// addresses and codes common to all cores +#define ADDR_NAME0 0x00 +#define ADDR_NAME1 0x01 +#define ADDR_VERSION 0x02 + + +// a handy macro from cryptlib +#ifndef bitsToBytes +#define bitsToBytes(x) (x / 8) +#endif + + +//------------------------------------------------------------------ +// Board segment. +// Board-level registers and communication channel registers +//------------------------------------------------------------------ +#define BOARD_CORE_SIZE 0x100 + +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0 * BOARD_CORE_SIZE) +#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 +#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 +#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION +#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + 0xFF + +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (1 * BOARD_CORE_SIZE) +#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 +#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 +#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION + + +//------------------------------------------------------------------ +// Hashes segment. +//------------------------------------------------------------------ +#define HASH_CORE_SIZE 0x100 + +// addresses and codes common to all hash cores +#define ADDR_CTRL 0x8 +#define CTRL_INIT_CMD 1 +#define CTRL_NEXT_CMD 2 +#define ADDR_STATUS 0x9 +#define STATUS_READY_BIT 1 +#define STATUS_VALID_BIT 2 +#define ADDR_BLOCK 0x10 +#define ADDR_DIGEST 0x20 // except SHA512 + +// addresses and codes for the specific hash cores. +#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0 * HASH_CORE_SIZE) +#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 +#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 +#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION +#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL +#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS +#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK +#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST +#define SHA1_BLOCK_LEN bitsToBytes(512) +#define SHA1_LENGTH_LEN bitsToBytes(64) +#define SHA1_DIGEST_LEN bitsToBytes(160) + +#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1 * HASH_CORE_SIZE) +#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 +#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 +#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION +#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL +#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS +#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK +#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST +#define SHA256_BLOCK_LEN bitsToBytes(512) +#define SHA256_LENGTH_LEN bitsToBytes(64) +#define SHA256_DIGEST_LEN bitsToBytes(256) + +#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2 * HASH_CORE_SIZE) +#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 +#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 +#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION +#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL +#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS +#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK +#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + 0x40 +#define SHA512_BLOCK_LEN bitsToBytes(1024) +#define SHA512_LENGTH_LEN bitsToBytes(128) +#define SHA512_224_DIGEST_LEN bitsToBytes(224) +#define SHA512_256_DIGEST_LEN bitsToBytes(256) +#define SHA384_DIGEST_LEN bitsToBytes(384) +#define SHA512_DIGEST_LEN bitsToBytes(512) +#define MODE_SHA_512_224 0 << 2 +#define MODE_SHA_512_256 1 << 2 +#define MODE_SHA_384 2 << 2 +#define MODE_SHA_512 3 << 2 + + +//----------------------------------------------------------------- +// TRNG segment. +//----------------------------------------------------------------- +#define TRNG_CORE_SIZE 0x100 + +// addresses and codes for the TRNG cores */ +#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0 * TRNG_CORE_SIZE) +#define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 +#define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 +#define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION +#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + 0x10 +#define TRNG_CTRL_DISCARD 1 +#define TRNG_CTRL_TEST_MODE 2 +#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + 0x11 +// no status bits defined (yet) +#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + 0x13 + +#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (5 * TRNG_CORE_SIZE) +#define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 +#define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 +#define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION +#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + 0x10 +#define ENTROPY1_CTRL_ENABLE 1 +#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + 0x11 +#define ENTROPY1_STATUS_VALID 1 +#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + 0x20 +#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + 0x30 + +#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (6 * TRNG_CORE_SIZE) +#define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 +#define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 +#define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION +#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + 0x10 +#define ENTROPY2_CTRL_ENABLE 1 +#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + 0x11 +#define ENTROPY2_STATUS_VALID 1 +#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + 0x18 +#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + 0x19 +#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + 0x20 +#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + 0x21 +#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + 0x22 + +#define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * TRNG_CORE_SIZE) +#define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 +#define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 +#define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION +#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + 0x10 +#define MIXER_CTRL_ENABLE 1 +#define MIXER_CTRL_RESTART 2 +#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + 0x11 +// no status bits defined (yet) +#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + 0x20 + +#define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * TRNG_CORE_SIZE) +#define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 +#define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 +#define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION +#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + 0x10 +#define CSPRNG_CTRL_ENABLE 1 +#define CSPRNG_CTRL_SEED 2 +#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + 0x11 +#define CSPRNG_STATUS_VALID 1 +#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + 0x20 +#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + 0x40 +#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + 0x41 +#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + 0x42 + + +//------------------------------------------------------------------ +// Test case public functions +//------------------------------------------------------------------ +void tc_set_debug(int onoff); +int tc_write(off_t offset, const uint8_t *buf, size_t len); +int tc_read(off_t offset, uint8_t *buf, size_t len); +int tc_expected(off_t offset, const uint8_t *expected, size_t len); +int tc_init(off_t offset); +int tc_next(off_t offset); +int tc_wait(off_t offset, uint8_t status, int *count); +int tc_wait_ready(off_t offset); +int tc_wait_valid(off_t offset); + + +//------------------------------------------------------------------ +// I2C configuration +// Only used in I2C, but not harmful to define for EIM +//------------------------------------------------------------------ +#define I2C_dev "/dev/i2c-2" +#define I2C_addr 0x0f +#define I2C_SLAVE 0x0703 + + +//====================================================================== +// EOF cryptech.h +//====================================================================== diff --git a/sw/hash.c b/sw/hash.c new file mode 100644 index 0000000..1b7d2cc --- /dev/null +++ b/sw/hash.c @@ -0,0 +1,291 @@ +/* + * hash.c + * ------ + * This program uses the coretest_hashes subsystem to produce a + * cryptographic hash of a file or input stream. It is a generalization + * of the hash_tester.c test program. + * + * Authors: Joachim Strömbergson, Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cryptech.h" + +char *usage = +"Usage: %s [-d] [-v] [-q] [algorithm [file]]\n" +"algorithms: sha-1, sha-256, sha-512/224, sha-512/256, sha-384, sha-512\n"; + +int quiet = 0; +int verbose = 0; + + +/* ---------------- algorithm lookup code ---------------- */ + +struct ctrl { + char *name; + off_t block_addr; + int block_len; + off_t digest_addr; + int digest_len; + int mode; +} ctrl[] = { + { "sha-1", SHA1_ADDR_BLOCK, SHA1_BLOCK_LEN, + SHA1_ADDR_DIGEST, SHA1_DIGEST_LEN, 0 }, + { "sha-256", SHA256_ADDR_BLOCK, SHA256_BLOCK_LEN, + SHA256_ADDR_DIGEST, SHA256_DIGEST_LEN, 0 }, + { "sha-512/224", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_224_DIGEST_LEN, MODE_SHA_512_224 }, + { "sha-512/256", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_256_DIGEST_LEN, MODE_SHA_512_256 }, + { "sha-384", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA384_DIGEST_LEN, MODE_SHA_384 }, + { "sha-512", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_DIGEST_LEN, MODE_SHA_512 }, + { NULL, 0, 0, 0 } +}; + +/* return the control structure for the given algorithm */ +struct ctrl *find_algo(char *algo) +{ + int i; + + for (i = 0; ctrl[i].name != NULL; ++i) + if (strcmp(ctrl[i].name, algo) == 0) + return &ctrl[i]; + + fprintf(stderr, "algorithm \"%s\" not found\n\n", algo); + fprintf(stderr, usage, "hash"); + return NULL; +} + +/* ---------------- hash ---------------- */ + +static int transmit(off_t offset, uint8_t *block, int blen, int mode, int first) +{ + off_t base = offset & ~(0x1ff); + uint8_t ctrl_cmd[4] = { 0 }; + + if (tc_write(offset, block, blen) != 0) + return 1; + + ctrl_cmd[3] = (first ? CTRL_INIT_CMD : CTRL_NEXT_CMD) | mode; + + return + tc_write(base + ADDR_CTRL, ctrl_cmd, 4) || + tc_wait_ready(base + ADDR_STATUS); +} + +static int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen, + uint8_t mode, long long tlen, int first) +{ + assert(flen < blen); + + block[flen++] = 0x80; + memset(block + flen, 0, blen - flen); + + if (blen - flen < ((blen == 64) ? 8 : 16)) { + if (transmit(offset, block, blen, mode, first) != 0) + return 1; + first = 0; + memset(block, 0, blen); + } + + /* properly the length is 128 bits for sha-512, but we can't + * actually count above 64 bits + */ + ((uint32_t *)block)[blen/4 - 2] = htonl((tlen >> 32) & 0xffff); + ((uint32_t *)block)[blen/4 - 1] = htonl(tlen & 0xffff); + + return transmit(offset, block, blen, mode, first); +} + +/* return number of digest bytes read */ +static int hash(char *algo, char *file, uint8_t *digest) +{ + uint8_t block[SHA512_BLOCK_LEN]; + struct ctrl *ctrl; + int in_fd = 0; /* stdin */ + off_t baddr, daddr; + int blen, dlen, mode; + int nblk, nread, first; + int ret = -1; + struct timeval start, stop, difftime; + + ctrl = find_algo(algo); + if (ctrl == NULL) + return -1; + baddr = ctrl->block_addr; + blen = ctrl->block_len; + daddr = ctrl->digest_addr; + dlen = ctrl->digest_len; + mode = ctrl->mode; + + if (strcmp(file, "-") != 0) { + in_fd = open(file, O_RDONLY); + if (in_fd < 0) { + perror("open"); + return -1; + } + } + + if (verbose) { + if (gettimeofday(&start, NULL) < 0) { + perror("gettimeofday"); + goto out; + } + } + + for (nblk = 0, first = 1; ; ++nblk, first = 0) { + nread = read(in_fd, block, blen); + if (nread < 0) { + /* read error */ + perror("read"); + goto out; + } + else if (nread < blen) { + /* partial read = last block */ + if (pad_transmit(baddr, block, nread, blen, mode, + (nblk * blen + nread) * 8, first) != 0) + goto out; + break; + } + else { + /* full block read */ + if (transmit(baddr, block, blen, mode, first) != 0) + goto out; + } + } + + /* Strictly speaking we should query "valid" status before reading digest, + * but transmit() waits for "ready" status before returning, and the SHA + * cores always assert valid before ready. + */ + if (tc_read(daddr, digest, dlen) != 0) { + perror("i2c read failed"); + goto out; + } + + if (verbose) { + if (gettimeofday(&stop, NULL) < 0) { + perror("gettimeofday"); + goto out; + } + timersub(&stop, &start, &difftime); + printf("%d blocks written in %d.%03d sec (%.3f blocks/sec)\n", + nblk, (int)difftime.tv_sec, (int)difftime.tv_usec/1000, + (float)nblk / ((float)difftime.tv_sec + ((float)difftime.tv_usec)/1000000)); + } + + ret = dlen; +out: + if (in_fd != 0) + close(in_fd); + return ret; +} + +/* ---------------- main ---------------- */ + +int main(int argc, char *argv[]) +{ + int i, opt; + char *algo = "sha-1"; + char *file = "-"; + uint8_t digest[512/8]; + int dlen; + + while ((opt = getopt(argc, argv, "h?dvq")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + tc_set_debug(1); + break; + case 'v': + verbose = 1; + break; + case 'q': + quiet = 1; + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + if (optind < argc) { + algo = argv[optind]; + ++optind; + } + else { + if (!quiet) + printf("defaulting to algorithm \"%s\"\n", algo); + } + + if (optind < argc) { + file = argv[optind]; + ++optind; + } + else { + if (!quiet) + printf("reading from stdin\n"); + } + + dlen = hash(algo, file, digest); + if (dlen < 0) + return EXIT_FAILURE; + + for (i = 0; i < dlen; ++i) { + printf("%02x", digest[i]); + if (i % 16 == 15) + printf("\n"); + else if (i % 4 == 3) + printf(" "); + } + if (dlen % 16 != 0) + printf("\n"); + + return EXIT_SUCCESS; +} diff --git a/sw/hash_tester.c b/sw/hash_tester.c new file mode 100644 index 0000000..6ddc09a --- /dev/null +++ b/sw/hash_tester.c @@ -0,0 +1,681 @@ +/* + * hash_tester.c + * -------------- + * This program sends several commands to the coretest_hashes subsystem + * in order to verify the SHA-1, SHA-256 and SHA-512/x hash function + * cores. + * + * Note: This version of the program talks to the FPGA over an EIM bus. + * + * The single and dual block test cases are taken from the + * NIST KAT document: + * http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf + * + * + * Authors: Joachim Strömbergson, Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cryptech.h" + +int quiet = 0; +int repeat = 0; + + +/* SHA-1/SHA-256 One Block Message Sample + Input Message: "abc" */ +const uint8_t NIST_512_SINGLE[] = +{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; + +const uint8_t SHA1_SINGLE_DIGEST[] = +{ 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, + 0xba, 0x3e, 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, + 0x9c, 0xd0, 0xd8, 0x9d }; + +const uint8_t SHA256_SINGLE_DIGEST[] = +{ 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, + 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, + 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, + 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }; + +/* SHA-1/SHA-256 Two Block Message Sample + Input Message: "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" */ +const uint8_t NIST_512_DOUBLE0[] = +{ 0x61, 0x62, 0x63, 0x64, 0x62, 0x63, 0x64, 0x65, + 0x63, 0x64, 0x65, 0x66, 0x64, 0x65, 0x66, 0x67, + 0x65, 0x66, 0x67, 0x68, 0x66, 0x67, 0x68, 0x69, + 0x67, 0x68, 0x69, 0x6A, 0x68, 0x69, 0x6A, 0x6B, + 0x69, 0x6A, 0x6B, 0x6C, 0x6A, 0x6B, 0x6C, 0x6D, + 0x6B, 0x6C, 0x6D, 0x6E, 0x6C, 0x6D, 0x6E, 0x6F, + 0x6D, 0x6E, 0x6F, 0x70, 0x6E, 0x6F, 0x70, 0x71, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +const uint8_t NIST_512_DOUBLE1[] = +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0 }; + +const uint8_t SHA1_DOUBLE_DIGEST[] = +{ 0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, + 0xBA, 0xAE, 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, + 0xE5, 0x46, 0x70, 0xF1 }; + +const uint8_t SHA256_DOUBLE_DIGEST[] = +{ 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, + 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, + 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, + 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }; + +/* SHA-512 One Block Message Sample + Input Message: "abc" */ +const uint8_t NIST_1024_SINGLE[] = +{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; + +const uint8_t SHA512_224_SINGLE_DIGEST[] = +{ 0x46, 0x34, 0x27, 0x0f, 0x70, 0x7b, 0x6a, 0x54, + 0xda, 0xae, 0x75, 0x30, 0x46, 0x08, 0x42, 0xe2, + 0x0e, 0x37, 0xed, 0x26, 0x5c, 0xee, 0xe9, 0xa4, + 0x3e, 0x89, 0x24, 0xaa }; +const uint8_t SHA512_256_SINGLE_DIGEST[] = +{ 0x53, 0x04, 0x8e, 0x26, 0x81, 0x94, 0x1e, 0xf9, + 0x9b, 0x2e, 0x29, 0xb7, 0x6b, 0x4c, 0x7d, 0xab, + 0xe4, 0xc2, 0xd0, 0xc6, 0x34, 0xfc, 0x6d, 0x46, + 0xe0, 0xe2, 0xf1, 0x31, 0x07, 0xe7, 0xaf, 0x23 }; +const uint8_t SHA384_SINGLE_DIGEST[] = +{ 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, + 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07, + 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, + 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23, + 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 }; +const uint8_t SHA512_SINGLE_DIGEST[] = +{ 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, + 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, + 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, + 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8, + 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, + 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f }; + +/* SHA-512 Two Block Message Sample + Input Message: "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" + "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" */ +const uint8_t NIST_1024_DOUBLE0[] = +{ 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, + 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, + 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, + 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, + 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, + 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, + 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, + 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, + 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, + 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +const uint8_t NIST_1024_DOUBLE1[] = +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80 }; + +const uint8_t SHA512_224_DOUBLE_DIGEST[] = +{ 0x23, 0xfe, 0xc5, 0xbb, 0x94, 0xd6, 0x0b, 0x23, + 0x30, 0x81, 0x92, 0x64, 0x0b, 0x0c, 0x45, 0x33, + 0x35, 0xd6, 0x64, 0x73, 0x4f, 0xe4, 0x0e, 0x72, + 0x68, 0x67, 0x4a, 0xf9 }; +const uint8_t SHA512_256_DOUBLE_DIGEST[] = +{ 0x39, 0x28, 0xe1, 0x84, 0xfb, 0x86, 0x90, 0xf8, + 0x40, 0xda, 0x39, 0x88, 0x12, 0x1d, 0x31, 0xbe, + 0x65, 0xcb, 0x9d, 0x3e, 0xf8, 0x3e, 0xe6, 0x14, + 0x6f, 0xea, 0xc8, 0x61, 0xe1, 0x9b, 0x56, 0x3a }; +const uint8_t SHA384_DOUBLE_DIGEST[] = +{ 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8, + 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47, + 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2, + 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12, + 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9, + 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 }; +const uint8_t SHA512_DOUBLE_DIGEST[] = +{ 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda, + 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f, + 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1, + 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18, + 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4, + 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a, + 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54, + 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 }; + +/* ---------------- sanity test case ---------------- */ + +int TC0() +{ + uint8_t board_name0[4] = "PVT1"; + uint8_t board_name1[4] = " "; + uint8_t board_version[4] = "0.10"; + + uint8_t comm_name0[4] = "eim "; + uint8_t comm_name1[4] = " "; + uint8_t comm_version[4] = "0.10"; + + uint8_t t[4]; + + if (!quiet) + printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); + + /* write current time into dummy register, then try to read it back + * to make sure that we can actually write something into EIM + */ + (void)time((time_t *)t); + if (tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4) != 0) + return 1; + + if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || + tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || + tc_expected(BOARD_ADDR_VERSION, board_version, 4) || + tc_expected(BOARD_ADDR_DUMMY, (void *)t, 4)) + return 1; + + if (!quiet) + printf("TC0-2: Reading name and version words from communications core.\n"); + + return + tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || + tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || + tc_expected(COMM_ADDR_VERSION, comm_version, 4); +} + +/* ---------------- SHA-1 test cases ---------------- */ + +/* TC1: Read name and version from SHA-1 core. */ +int TC1(void) +{ + uint8_t name0[4] = "sha1"; + uint8_t name1[4] = " "; + uint8_t version[4] = "0.50"; + + if (!quiet) + printf("TC1: Reading name and version words from SHA-1 core.\n"); + + return + tc_expected(SHA1_ADDR_NAME0, name0, 4) || + tc_expected(SHA1_ADDR_NAME1, name1, 4) || + tc_expected(SHA1_ADDR_VERSION, version, 4); +} + +/* TC2: SHA-1 Single block message test as specified by NIST. */ +int TC2(void) +{ + const uint8_t *block = NIST_512_SINGLE; + const uint8_t *expected = SHA1_SINGLE_DIGEST; + int ret; + + if (!quiet) + printf("TC2: Single block message test for SHA-1.\n"); + + /* Write block to SHA-1. */ + tc_write(SHA1_ADDR_BLOCK, block, SHA1_BLOCK_LEN); + /* Start initial block hashing, wait and check status. */ + tc_init(SHA1_ADDR_CTRL); + tc_wait_valid(SHA1_ADDR_STATUS); + /* Extract the digest. */ + ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); + return ret; +} + +/* TC3: SHA-1 Double block message test as specified by NIST. */ +int TC3(void) +{ + const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; + static const uint8_t block0_expected[] = + { 0xF4, 0x28, 0x68, 0x18, 0xC3, 0x7B, 0x27, 0xAE, + 0x04, 0x08, 0xF5, 0x81, 0x84, 0x67, 0x71, 0x48, + 0x4A, 0x56, 0x65, 0x72 }; + const uint8_t *expected = SHA1_DOUBLE_DIGEST; + int ret; + + if (!quiet) + printf("TC3: Double block message test for SHA-1.\n"); + + /* Write first block to SHA-1. */ + tc_write(SHA1_ADDR_BLOCK, block[0], SHA1_BLOCK_LEN); + /* Start initial block hashing, wait and check status. */ + tc_init(SHA1_ADDR_CTRL); + tc_wait_valid(SHA1_ADDR_STATUS); + /* Extract the first digest. */ + tc_expected(SHA1_ADDR_DIGEST, block0_expected, SHA1_DIGEST_LEN); + /* Write second block to SHA-1. */ + tc_write(SHA1_ADDR_BLOCK, block[1], SHA1_BLOCK_LEN); + /* Start next block hashing, wait and check status. */ + tc_next(SHA1_ADDR_CTRL); + tc_wait_valid(SHA1_ADDR_STATUS); + /* Extract the second digest. */ + ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); + return ret; +} + +/* ---------------- SHA-256 test cases ---------------- */ + +/* TC4: Read name and version from SHA-256 core. */ +int TC4(void) +{ + uint8_t name0[4] = "sha2"; + uint8_t name1[4] = "-256"; + uint8_t version[4] = "0.80"; + + if (!quiet) + printf("TC4: Reading name, type and version words from SHA-256 core.\n"); + + return + tc_expected(SHA256_ADDR_NAME0, name0, 4) || + tc_expected(SHA256_ADDR_NAME1, name1, 4) || + tc_expected(SHA256_ADDR_VERSION, version, 4); +} + +/* TC5: SHA-256 Single block message test as specified by NIST. */ +int TC5() +{ + const uint8_t *block = NIST_512_SINGLE; + const uint8_t *expected = SHA256_SINGLE_DIGEST; + + if (!quiet) + printf("TC5: Single block message test for SHA-256.\n"); + + return + /* Write block to SHA-256. */ + tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_init(SHA256_ADDR_CTRL) || + tc_wait_valid(SHA256_ADDR_STATUS) || + /* Extract the digest. */ + tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); +} + +/* TC6: SHA-256 Double block message test as specified by NIST. */ +int TC6() +{ + const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; + static const uint8_t block0_expected[] = + { 0x85, 0xE6, 0x55, 0xD6, 0x41, 0x7A, 0x17, 0x95, + 0x33, 0x63, 0x37, 0x6A, 0x62, 0x4C, 0xDE, 0x5C, + 0x76, 0xE0, 0x95, 0x89, 0xCA, 0xC5, 0xF8, 0x11, + 0xCC, 0x4B, 0x32, 0xC1, 0xF2, 0x0E, 0x53, 0x3A }; + const uint8_t *expected = SHA256_DOUBLE_DIGEST; + + if (!quiet) + printf("TC6: Double block message test for SHA-256.\n"); + + return + /* Write first block to SHA-256. */ + tc_write(SHA256_ADDR_BLOCK, block[0], SHA256_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_init(SHA256_ADDR_CTRL) || + tc_wait_valid(SHA256_ADDR_STATUS) || + /* Extract the first digest. */ + tc_expected(SHA256_ADDR_DIGEST, block0_expected, SHA256_DIGEST_LEN) || + /* Write second block to SHA-256. */ + tc_write(SHA256_ADDR_BLOCK, block[1], SHA256_BLOCK_LEN) || + /* Start next block hashing, wait and check status. */ + tc_next(SHA256_ADDR_CTRL) || + tc_wait_valid(SHA256_ADDR_STATUS) || + /* Extract the second digest. */ + tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); +} + +/* TC7: SHA-256 Huge message test. */ +int TC7() +{ + static const uint8_t block[] = + { 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, + 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, + 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, + 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f }; + + /* final digest after 1000 iterations */ + static const uint8_t expected[] = + { 0x76, 0x38, 0xf3, 0xbc, 0x50, 0x0d, 0xd1, 0xa6, + 0x58, 0x6d, 0xd4, 0xd0, 0x1a, 0x15, 0x51, 0xaf, + 0xd8, 0x21, 0xd2, 0x35, 0x2f, 0x91, 0x9e, 0x28, + 0xd5, 0x84, 0x2f, 0xab, 0x03, 0xa4, 0x0f, 0x2a }; + + int i, n = 1000; + + if (!quiet) + printf("TC7: Message with %d blocks test for SHA-256.\n", n); + + /* Write block data to SHA-256. */ + if (tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN)) + return 1; + + /* Start initial block hashing, wait and check status. */ + if (tc_init(SHA256_ADDR_CTRL) || + tc_wait_ready(SHA256_ADDR_STATUS)) + return 1; + + /* First block done. Do the rest. */ + for (i = 1; i < n; ++i) { + /* Start next block hashing, wait and check status. */ + if (tc_next(SHA256_ADDR_CTRL) || + tc_wait_ready(SHA256_ADDR_STATUS)) + return 1; + } + + /* XXX valid is probably set at the same time as ready */ + if (tc_wait_valid(SHA256_ADDR_STATUS)) + return 1; + /* Extract the final digest. */ + return tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); +} + +/* ---------------- SHA-512 test cases ---------------- */ + +/* TC8: Read name and version from SHA-512 core. */ +int TC8() +{ + uint8_t name0[4] = "sha2"; + uint8_t name1[4] = "-512"; + uint8_t version[4] = "0.80"; + + if (!quiet) + printf("TC8: Reading name, type and version words from SHA-512 core.\n"); + + return + tc_expected(SHA512_ADDR_NAME0, name0, 4) || + tc_expected(SHA512_ADDR_NAME1, name1, 4) || + tc_expected(SHA512_ADDR_VERSION, version, 4); +} + +/* TC9: SHA-512 Single block message test as specified by NIST. + We do this for all modes. */ +int tc9(int mode, const uint8_t *expected, int digest_len) +{ + const uint8_t *block = NIST_1024_SINGLE; + uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; + + return + /* Write block to SHA-512. */ + tc_write(SHA512_ADDR_BLOCK, block, SHA512_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_write(SHA512_ADDR_CTRL, init, 4) || + tc_wait_valid(SHA512_ADDR_STATUS) || + /* Extract the digest. */ + tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); +} + +int TC9() +{ + if (!quiet) + printf("TC9-1: Single block message test for SHA-512/224.\n"); + if (tc9(MODE_SHA_512_224, SHA512_224_SINGLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC9-2: Single block message test for SHA-512/256.\n"); + if (tc9(MODE_SHA_512_256, SHA512_256_SINGLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC9-3: Single block message test for SHA-384.\n"); + if (tc9(MODE_SHA_384, SHA384_SINGLE_DIGEST, SHA384_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC9-4: Single block message test for SHA-512.\n"); + if (tc9(MODE_SHA_512, SHA512_SINGLE_DIGEST, SHA512_DIGEST_LEN) != 0) + return 1; + + return 0; +} + +/* TC10: SHA-512 Double block message test as specified by NIST. + We do this for all modes. */ +int tc10(int mode, const uint8_t *expected, int digest_len) +{ + const uint8_t *block[2] = { NIST_1024_DOUBLE0, NIST_1024_DOUBLE1 }; + uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; + uint8_t next[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode }; + + return + /* Write first block to SHA-512. */ + tc_write(SHA512_ADDR_BLOCK, block[0], SHA512_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_write(SHA512_ADDR_CTRL, init, 4) || + tc_wait_ready(SHA512_ADDR_STATUS) || + /* Write second block to SHA-512. */ + tc_write(SHA512_ADDR_BLOCK, block[1], SHA512_BLOCK_LEN) || + /* Start next block hashing, wait and check status. */ + tc_write(SHA512_ADDR_CTRL, next, 4) || + tc_wait_valid(SHA512_ADDR_STATUS) || + /* Extract the digest. */ + tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); +} + +int TC10() +{ + if (!quiet) + printf("TC10-1: Double block message test for SHA-512/224.\n"); + if (tc10(MODE_SHA_512_224, SHA512_224_DOUBLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC10-2: Double block message test for SHA-512/256.\n"); + if (tc10(MODE_SHA_512_256, SHA512_256_DOUBLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC10-3: Double block message test for SHA-384.\n"); + if (tc10(MODE_SHA_384, SHA384_DOUBLE_DIGEST, SHA384_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC10-4: Double block message test for SHA-512.\n"); + if (tc10(MODE_SHA_512, SHA512_DOUBLE_DIGEST, SHA512_DIGEST_LEN) != 0) + return 1; + + return 0; +} + +/* ---------------- main ---------------- */ + +/* signal handler for ctrl-c to end repeat testing */ +unsigned long iter = 0; +struct timeval tv_start, tv_end; +void sighandler(int unused) +{ + double tv_diff; + + gettimeofday(&tv_end, NULL); + tv_diff = (double)(tv_end.tv_sec - tv_start.tv_sec) + + (double)(tv_end.tv_usec - tv_start.tv_usec)/1000000; + printf("\n%lu iterations in %.3f seconds (%.3f iterations/sec)\n", + iter, tv_diff, (double)iter/tv_diff); + exit(EXIT_SUCCESS); +} + +int main(int argc, char *argv[]) +{ + typedef int (*tcfp)(void); + tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7, TC8, TC9, TC10 }; + tcfp sha1_tests[] = { TC1, TC2, TC3 }; + tcfp sha256_tests[] = { TC4, TC5, TC6, TC7 }; + tcfp sha512_tests[] = { TC8, TC9, TC10 }; + + char *usage = "Usage: %s [-h] [-d] [-q] [-r] tc...\n"; + int i, j, opt; + + while ((opt = getopt(argc, argv, "h?dqr")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + tc_set_debug(1); + break; + case 'q': + quiet = 1; + break; + case 'r': + repeat = 1; + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + /* repeat one test until interrupted */ + if (repeat) { + tcfp tc; + if (optind != argc - 1) { + fprintf(stderr, "only one test case can be repeated\n"); + return EXIT_FAILURE; + } + j = atoi(argv[optind]); + if (j < 0 || j >= sizeof(all_tests)/sizeof(all_tests[0])) { + fprintf(stderr, "invalid test number %s\n", argv[optind]); + return EXIT_FAILURE; + } + tc = (all_tests[j]); + srand(time(NULL)); + signal(SIGINT, sighandler); + gettimeofday(&tv_start, NULL); + while (1) { + ++iter; + if ((iter & 0xffff) == 0) { + printf("."); + fflush(stdout); + } + if (tc() != 0) + sighandler(0); + } + return EXIT_SUCCESS; /*NOTREACHED*/ + } + + /* no args == run all tests */ + if (optind >= argc) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + return EXIT_SUCCESS; + } + + /* run one or more tests (by number) or groups of tests (by name) */ + for (i = optind; i < argc; ++i) { + if (strcmp(argv[i], "all") == 0) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (strcmp(argv[i], "sha1") == 0) { + for (j = 0; j < sizeof(sha1_tests)/sizeof(sha1_tests[0]); ++j) + if (sha1_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (strcmp(argv[i], "sha256") == 0) { + for (j = 0; j < sizeof(sha256_tests)/sizeof(sha256_tests[0]); ++j) + if (sha256_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (strcmp(argv[i], "sha512") == 0) { + for (j = 0; j < sizeof(sha512_tests)/sizeof(sha512_tests[0]); ++j) + if (sha512_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (isdigit(argv[i][0]) && + (((j = atoi(argv[i])) >= 0) && + (j < sizeof(all_tests)/sizeof(all_tests[0])))) { + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else { + fprintf(stderr, "unknown test case %s\n", argv[i]); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} diff --git a/sw/novena-eim.c b/sw/novena-eim.c new file mode 100644 index 0000000..85bfac0 --- /dev/null +++ b/sw/novena-eim.c @@ -0,0 +1,708 @@ +/* + * novena-eim.c + * ------------ + * This module contains the userland magic to set up and use the EIM bus. + * + * + * Author: Pavel Shatov + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ +#include +#include +#include +#include +#include +#include +#include + +#include "novena-eim.h" + + +//------------------------------------------------------------------------------ +// Defines +//------------------------------------------------------------------------------ +#define MEMORY_DEVICE "/dev/mem" + +#define IOMUXC_MUX_MODE_ALT0 0 // 000 + +#define IOMUXC_PAD_CTL_SRE_FAST 1 // 1 +#define IOMUXC_PAD_CTL_DSE_33_OHM 7 // 111 +#define IOMUXC_PAD_CTL_SPEED_MEDIUM_10 2 // 10 +#define IOMUXC_PAD_CTL_ODE_DISABLED 0 // 0 +#define IOMUXC_PAD_CTL_PKE_DISABLED 0 // 0 +#define IOMUXC_PAD_CTL_PUE_PULL 1 // 1 +#define IOMUXC_PAD_CTL_PUS_100K_OHM_PU 2 // 10 +#define IOMUXC_PAD_CTL_HYS_DISABLED 0 // 0 + +#define CCM_CGR_OFF 0 // 00 +#define CCM_CGR_ON_EXCEPT_STOP 3 // 11 + + +//------------------------------------------------------------------------------ +// CPU Registers +//------------------------------------------------------------------------------ +enum IMX6DQ_REGISTER_OFFSET +{ + IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B = 0x020E00F8, + IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B = 0x020E0100, + IOMUXC_SW_MUX_CTL_PAD_EIM_RW = 0x020E0104, + IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B = 0x020E0108, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 = 0x020E0114, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 = 0x020E0118, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 = 0x020E011C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 = 0x020E0120, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 = 0x020E0124, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 = 0x020E0128, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 = 0x020E012C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 = 0x020E0130, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 = 0x020E0134, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 = 0x020E0138, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 = 0x020E013C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 = 0x020E0140, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 = 0x020E0144, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 = 0x020E0148, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 = 0x020E014C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 = 0x020E0150, + IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B = 0x020E0154, + IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK = 0x020E0158, + + IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B = 0x020E040C, + IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B = 0x020E0414, + IOMUXC_SW_PAD_CTL_PAD_EIM_RW = 0x020E0418, + IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B = 0x020E041C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 = 0x020E0428, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 = 0x020E042C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 = 0x020E0430, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 = 0x020E0434, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 = 0x020E0438, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 = 0x020E043C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 = 0x020E0440, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 = 0x020E0444, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 = 0x020E0448, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 = 0x020E044C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 = 0x020E0450, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 = 0x020E0454, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 = 0x020E0458, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 = 0x020E045C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 = 0x020E0460, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 = 0x020E0464, + IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B = 0x020E0468, + IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK = 0x020E046C, + + CCM_CCGR6 = 0x020C4080, + + EIM_CS0GCR1 = 0x021B8000, + EIM_CS0GCR2 = 0x021B8004, + EIM_CS0RCR1 = 0x021B8008, + EIM_CS0RCR2 = 0x021B800C, + EIM_CS0WCR1 = 0x021B8010, + EIM_CS0WCR2 = 0x021B8014, + + EIM_WCR = 0x021B8090, + EIM_WIAR = 0x021B8094, + EIM_EAR = 0x021B8098, +}; + + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ +struct IOMUXC_SW_MUX_CTL_PAD_EIM +{ + unsigned int mux_mode : 3; + unsigned int reserved_3 : 1; + unsigned int sion : 1; + unsigned int reserved_31_5 : 27; +}; + +struct IOMUXC_SW_PAD_CTL_PAD_EIM +{ + unsigned int sre : 1; + unsigned int reserved_2_1 : 2; + unsigned int dse : 3; + unsigned int speed : 2; + unsigned int reserved_10_8 : 3; + unsigned int ode : 1; + unsigned int pke : 1; + unsigned int pue : 1; + unsigned int pus : 2; + unsigned int hys : 1; + unsigned int reserved_31_17 : 15; +}; + +struct CCM_CCGR6 +{ + unsigned int cg0_usboh3 : 2; + unsigned int cg1_usdhc1 : 2; + unsigned int cg2_usdhc2 : 2; + unsigned int cg3_usdhc3 : 2; + + unsigned int cg3_usdhc4 : 2; + unsigned int cg5_eim_slow : 2; + unsigned int cg6_vdoaxiclk : 2; + unsigned int cg7_vpu : 2; + + unsigned int cg8_reserved : 2; + unsigned int cg9_reserved : 2; + unsigned int cg10_reserved : 2; + unsigned int cg11_reserved : 2; + + unsigned int cg12_reserved : 2; + unsigned int cg13_reserved : 2; + unsigned int cg14_reserved : 2; + unsigned int cg15_reserved : 2; +}; + +struct EIM_CS_GCR1 +{ + unsigned int csen : 1; + unsigned int swr : 1; + unsigned int srd : 1; + unsigned int mum : 1; + unsigned int wfl : 1; + unsigned int rfl : 1; + unsigned int cre : 1; + unsigned int crep : 1; + unsigned int bl : 3; + unsigned int wc : 1; + unsigned int bcd : 2; + unsigned int bcs : 2; + unsigned int dsz : 3; + unsigned int sp : 1; + unsigned int csrec : 3; + unsigned int aus : 1; + unsigned int gbc : 3; + unsigned int wp : 1; + unsigned int psz : 4; +}; + +struct EIM_CS_GCR2 +{ + unsigned int adh : 2; + unsigned int reserved_3_2 : 2; + unsigned int daps : 4; + unsigned int dae : 1; + unsigned int dap : 1; + unsigned int reserved_11_10 : 2; + unsigned int mux16_byp_grant : 1; + unsigned int reserved_31_13 : 19; +}; + +struct EIM_CS_RCR1 +{ + unsigned int rcsn : 3; + unsigned int reserved_3 : 1; + unsigned int rcsa : 3; + unsigned int reserved_7 : 1; + unsigned int oen : 3; + unsigned int reserved_11 : 1; + unsigned int oea : 3; + unsigned int reserved_15 : 1; + unsigned int radvn : 3; + unsigned int ral : 1; + unsigned int radva : 3; + unsigned int reserved_23 : 1; + unsigned int rwsc : 6; + unsigned int reserved_31_30 : 2; +}; + +struct EIM_CS_RCR2 +{ + unsigned int rben : 3; + unsigned int rbe : 1; + unsigned int rbea : 3; + unsigned int reserved_7 : 1; + unsigned int rl : 2; + unsigned int reserved_11_10 : 2; + unsigned int pat : 3; + unsigned int apr : 1; + unsigned int reserved_31_16 : 16; +}; + +struct EIM_CS_WCR1 +{ + unsigned int wcsn : 3; + unsigned int wcsa : 3; + unsigned int wen : 3; + unsigned int wea : 3; + unsigned int wben : 3; + unsigned int wbea : 3; + unsigned int wadvn : 3; + unsigned int wadva : 3; + unsigned int wwsc : 6; + unsigned int wbed : 1; + unsigned int wal : 1; +}; + +struct EIM_CS_WCR2 +{ + unsigned int wbcdd : 1; + unsigned int reserved_31_1 : 31; +}; + +struct EIM_WCR +{ + unsigned int bcm : 1; + unsigned int gbcd : 2; + unsigned int reserved_3 : 1; + unsigned int inten : 1; + unsigned int intpol : 1; + unsigned int reserved_7_6 : 2; + unsigned int wdog_en : 1; + unsigned int wdog_limit : 2; + unsigned int reserved_31_11 : 21; +}; + +struct EIM_WIAR +{ + unsigned int ips_req : 1; + unsigned int ips_ack : 1; + unsigned int irq : 1; + unsigned int errst : 1; + unsigned int aclk_en : 1; + unsigned int reserved_31_5 : 27; +}; + +struct EIM_EAR +{ + unsigned int error_addr : 32; +}; + + +//------------------------------------------------------------------------------ +// Variables +//------------------------------------------------------------------------------ +static long mem_page_size = 0; +static int mem_dev_fd = -1; +static void * mem_map_ptr = MAP_FAILED; +static off_t mem_base_addr = 0; + + +//------------------------------------------------------------------------------ +// Prototypes +//------------------------------------------------------------------------------ +static void _eim_setup_iomuxc (void); +static void _eim_setup_ccm (void); +static void _eim_setup_eim (void); +static void _eim_cleanup (void); +static off_t _eim_calc_offset (off_t); +static void _eim_remap_mem (off_t); + + +//------------------------------------------------------------------------------ +// Set up EIM bus. Returns 0 on success, -1 on failure. +//------------------------------------------------------------------------------ +int eim_setup(void) +{ + // register cleanup function + if (atexit(_eim_cleanup) != 0) { + fprintf(stderr, "ERROR: atexit() failed.\n"); + return -1; + } + + // determine memory page size to use in mmap() + mem_page_size = sysconf(_SC_PAGESIZE); + if (mem_page_size < 1) { + fprintf(stderr, "ERROR: sysconf(_SC_PAGESIZE) == %ld\n", mem_page_size); + return -1; + } + + // try to open memory device + mem_dev_fd = open(MEMORY_DEVICE, O_RDWR | O_SYNC); + if (mem_dev_fd == -1) { + fprintf(stderr, "ERROR: open(%s) failed.\n", MEMORY_DEVICE); + return -1; + } + + // configure IOMUXC + _eim_setup_iomuxc(); + + // configure Clock Controller Module + _eim_setup_ccm(); + + /* We need to properly configure EIM mode and all the corresponding parameters. + * That's a lot of code, let's do it now. + */ + _eim_setup_eim(); + + // done + return 0; +} + + +//------------------------------------------------------------------------------ +// Shut down EIM bus. This is called automatically on exit(). +//------------------------------------------------------------------------------ +static void _eim_cleanup(void) +{ + // unmap memory if needed + if (mem_map_ptr != MAP_FAILED) + if (munmap(mem_map_ptr, mem_page_size) != 0) + fprintf(stderr, "WARNING: munmap() failed.\n"); + + // close memory device if needed + if (mem_dev_fd != -1) + if (close(mem_dev_fd) != 0) + fprintf(stderr, "WARNING: close() failed.\n"); +} + + +//------------------------------------------------------------------------------ +// Several blocks in the CPU have common pins. We use the I/O MUX Controller +// to configure what block will actually use I/O pins. We wait for the EIM +// module to be able to communicate with the on-board FPGA. +//------------------------------------------------------------------------------ +static void _eim_setup_iomuxc(void) +{ + // create structures + struct IOMUXC_SW_MUX_CTL_PAD_EIM reg_mux; // mux control register + struct IOMUXC_SW_PAD_CTL_PAD_EIM reg_pad; // pad control register + + // setup mux control register + reg_mux.mux_mode = IOMUXC_MUX_MODE_ALT0; // ALT0 mode must be used for EIM + reg_mux.sion = 0; // forced input not needed + reg_mux.reserved_3 = 0; // must be 0 + reg_mux.reserved_31_5 = 0; // must be 0 + + // setup pad control register + reg_pad.sre = IOMUXC_PAD_CTL_SRE_FAST; // fast slew rate + reg_pad.dse = IOMUXC_PAD_CTL_DSE_33_OHM; // highest drive strength + reg_pad.speed = IOMUXC_PAD_CTL_SPEED_MEDIUM_10; // medium speed + reg_pad.ode = IOMUXC_PAD_CTL_ODE_DISABLED; // open drain not needed + reg_pad.pke = IOMUXC_PAD_CTL_PKE_DISABLED; // neither pull nor keeper are needed + reg_pad.pue = IOMUXC_PAD_CTL_PUE_PULL; // doesn't matter actually, because PKE is disabled + reg_pad.pus = IOMUXC_PAD_CTL_PUS_100K_OHM_PU; // doesn't matter actually, because PKE is disabled + reg_pad.hys = IOMUXC_PAD_CTL_HYS_DISABLED; // use CMOS, not Schmitt trigger input + reg_pad.reserved_2_1 = 0; // must be 0 + reg_pad.reserved_10_8 = 0; // must be 0 + reg_pad.reserved_31_17 = 0; // must be 0 + + // all the pins must be configured to use the same ALT0 mode + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_RW, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD00, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD01, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD02, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD03, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD04, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD05, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD06, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD07, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD08, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD09, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD10, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD11, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD12, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD13, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD14, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD15, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK, (uint32_t *)®_mux); + + // we need to configure all the I/O pads too + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_RW, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, (uint32_t *)®_pad); +} + + +//------------------------------------------------------------------------------ +// Configure Clock Controller Module to enable clocking of EIM block. +//------------------------------------------------------------------------------ +static void _eim_setup_ccm(void) +{ + // create structure + struct CCM_CCGR6 ccm_ccgr6; + + // read register + eim_read_32(CCM_CCGR6, (uint32_t *)&ccm_ccgr6); + + // modify register + ccm_ccgr6.cg0_usboh3 = CCM_CGR_ON_EXCEPT_STOP; + ccm_ccgr6.cg1_usdhc1 = CCM_CGR_OFF; + ccm_ccgr6.cg2_usdhc2 = CCM_CGR_ON_EXCEPT_STOP; + ccm_ccgr6.cg3_usdhc3 = CCM_CGR_ON_EXCEPT_STOP; + + ccm_ccgr6.cg3_usdhc4 = CCM_CGR_OFF; + ccm_ccgr6.cg5_eim_slow = CCM_CGR_ON_EXCEPT_STOP; + ccm_ccgr6.cg6_vdoaxiclk = CCM_CGR_OFF; + ccm_ccgr6.cg7_vpu = CCM_CGR_OFF; + + ccm_ccgr6.cg8_reserved = 0; + ccm_ccgr6.cg9_reserved = 0; + ccm_ccgr6.cg10_reserved = 0; + ccm_ccgr6.cg11_reserved = 0; + ccm_ccgr6.cg12_reserved = 0; + ccm_ccgr6.cg13_reserved = 0; + ccm_ccgr6.cg14_reserved = 0; + ccm_ccgr6.cg15_reserved = 0; + + // write register + eim_write_32(CCM_CCGR6, (uint32_t *)&ccm_ccgr6); +} + + +//------------------------------------------------------------------------------ +// Configure EIM mode and all the corresponding parameters. That's a lot of code. +//------------------------------------------------------------------------------ +static void _eim_setup_eim(void) +{ + // create structures + struct EIM_CS_GCR1 gcr1; + struct EIM_CS_GCR2 gcr2; + struct EIM_CS_RCR1 rcr1; + struct EIM_CS_RCR2 rcr2; + struct EIM_CS_WCR1 wcr1; + struct EIM_CS_WCR2 wcr2; + + struct EIM_WCR wcr; + struct EIM_WIAR wiar; + struct EIM_EAR ear; + + // read all the registers + eim_read_32(EIM_CS0GCR1, (uint32_t *)&gcr1); + eim_read_32(EIM_CS0GCR2, (uint32_t *)&gcr2); + eim_read_32(EIM_CS0RCR1, (uint32_t *)&rcr1); + eim_read_32(EIM_CS0RCR2, (uint32_t *)&rcr2); + eim_read_32(EIM_CS0WCR1, (uint32_t *)&wcr1); + eim_read_32(EIM_CS0WCR2, (uint32_t *)&wcr2); + + eim_read_32(EIM_WCR, (uint32_t *)&wcr); + eim_read_32(EIM_WIAR, (uint32_t *)&wiar); + eim_read_32(EIM_EAR, (uint32_t *)&ear); + + // manipulate registers as needed + gcr1.csen = 1; // chip select is enabled + gcr1.swr = 1; // write is sync + gcr1.srd = 1; // read is sync + gcr1.mum = 1; // address and data are multiplexed + gcr1.wfl = 0; // write latency is not fixed + gcr1.rfl = 0; // read latency is not fixed + gcr1.cre = 0; // CRE signal not needed + //gcr1.crep = x; // don't care, CRE not used + gcr1.bl = 4; // burst length + gcr1.wc = 0; // write is not continuous + gcr1.bcd = 3; // BCLK divisor is 3+1=4 + gcr1.bcs = 1; // delay from ~CS to BCLK is 1 cycle + gcr1.dsz = 1; // 16 bits per databeat at DATA[15:0] + gcr1.sp = 0; // supervisor protection is disabled + gcr1.csrec = 1; // ~CS recovery is 1 cycle + gcr1.aus = 1; // address is not shifted + gcr1.gbc = 1; // ~CS gap is 1 cycle + gcr1.wp = 0; // write protection is not enabled + //gcr1.psz = x; // don't care, page mode is not used + + gcr2.adh = 0; // address hold duration is 1 cycle + //gcr2.daps = x; // don't care, DTACK is not used + gcr2.dae = 0; // DTACK is not used + //gcr2.dap = x; // don't care, DTACK is not used + gcr2.mux16_byp_grant= 1; // enable grant mechanism + gcr2.reserved_3_2 = 0; // must be 0 + gcr2.reserved_11_10 = 0; // must be 0 + gcr2.reserved_31_13 = 0; // must be 0 + + //rcr1.rcsn = x; // don't care in sync mode + rcr1.rcsa = 0; // no delay for ~CS needed + //rcr1.oen = x; // don't care in sync mode + rcr1.oea = 0; // no delay for ~OE needed + rcr1.radvn = 0; // no delay for ~LBA needed + rcr1.ral = 0; // clear ~LBA when needed + rcr1.radva = 0; // no delay for ~LBA needed + rcr1.rwsc = 1; // one wait state + rcr1.reserved_3 = 0; // must be 0 + rcr1.reserved_7 = 0; // must be 0 + rcr1.reserved_11 = 0; // must be 0 + rcr1.reserved_15 = 0; // must be 0 + rcr1.reserved_23 = 0; // must be 0 + rcr1.reserved_31_30 = 0; // must be 0 + + //rcr2.rben = x; // don't care in sync mode + rcr2.rbe = 0; // BE is disabled + //rcr2.rbea = x; // don't care when BE is not used + rcr2.rl = 0; // read latency is 0 + //rcr2.pat = x; // don't care when page read is not used + rcr2.apr = 0; // page read mode is not used + rcr2.reserved_7 = 0; // must be 0 + rcr2.reserved_11_10 = 0; // must be 0 + rcr2.reserved_31_16 = 0; // must be 0 + + //wcr1.wcsn = x; // don't care in sync mode + wcr1.wcsa = 0; // no delay for ~CS needed + //wcr1.wen = x; // don't care in sync mode + wcr1.wea = 0; // no delay for ~WR_N needed + //wcr1.wben = x; // don't care in sync mode + //wcr1.wbea = x; // don't care in sync mode + wcr1.wadvn = 0; // no delay for ~LBA needed + wcr1.wadva = 0; // no delay for ~LBA needed + wcr1.wwsc = 1; // no wait state in needed + wcr1.wbed = 1; // BE is disabled + wcr1.wal = 0; // clear ~LBA when needed + + wcr2.wbcdd = 0; // write clock division is not needed + wcr2.reserved_31_1 = 0; // must be 0 + + wcr.bcm = 0; // clock is only active during access + //wcr.gbcd = x; // don't care when BCM=0 + wcr.inten = 0; // interrupt is not used + //wcr.intpol = x; // don't care when interrupt is not used + wcr.wdog_en = 1; // watchdog is enabled + wcr.wdog_limit = 00; // timeout is 128 BCLK cycles + wcr.reserved_3 = 0; // must be 0 + wcr.reserved_7_6 = 0; // must be 0 + wcr.reserved_31_11 = 0; // must be 0 + + wiar.ips_req = 0; // IPS not needed + wiar.ips_ack = 0; // IPS not needed + //wiar.irq = x; // don't touch + //wiar.errst = x; // don't touch + wiar.aclk_en = 1; // clock is enabled + wiar.reserved_31_5 = 0; // must be 0 + + //ear.error_addr = x; // read-only + + // write modified registers + eim_write_32(EIM_CS0GCR1, (uint32_t *)&gcr1); + eim_write_32(EIM_CS0GCR2, (uint32_t *)&gcr2); + eim_write_32(EIM_CS0RCR1, (uint32_t *)&rcr1); + eim_write_32(EIM_CS0RCR2, (uint32_t *)&rcr2); + eim_write_32(EIM_CS0WCR1, (uint32_t *)&wcr1); + eim_write_32(EIM_CS0WCR2, (uint32_t *)&wcr2); + eim_write_32(EIM_WCR, (uint32_t *)&wcr); + eim_write_32(EIM_WIAR, (uint32_t *)&wiar); +/* eim_write_32(EIM_EAR, (uint32_t *)&ear);*/ +} + + +//------------------------------------------------------------------------------ +// Write a 32-bit word to EIM. +// If EIM is not set up correctly, this will abort with a bus error. +//------------------------------------------------------------------------------ +void eim_write_32(off_t offset, uint32_t *pvalue) +{ + // calculate memory offset + uint32_t *ptr = (uint32_t *)_eim_calc_offset(offset); + + // write data to memory + memcpy(ptr, pvalue, sizeof(uint32_t)); +} + +//------------------------------------------------------------------------------ +// Read a 32-bit word from EIM. +// If EIM is not set up correctly, this will abort with a bus error. +//------------------------------------------------------------------------------ +void eim_read_32(off_t offset, uint32_t *pvalue) +{ + // calculate memory offset + uint32_t *ptr = (uint32_t *)_eim_calc_offset(offset); + + // read data from memory + memcpy(pvalue, ptr, sizeof(uint32_t)); +} + + +//------------------------------------------------------------------------------ +// Calculate an offset into the currently-mapped EIM page. +//------------------------------------------------------------------------------ +static off_t _eim_calc_offset(off_t offset) +{ + // make sure that memory is mapped + if (mem_map_ptr == MAP_FAILED) + _eim_remap_mem(offset); + + // calculate starting and ending addresses of currently mapped page + off_t offset_low = mem_base_addr; + off_t offset_high = mem_base_addr + (mem_page_size - 1); + + // check that offset is in currently mapped page, remap new page otherwise + if ((offset < offset_low) || (offset > offset_high)) + _eim_remap_mem(offset); + + // calculate pointer + return (off_t)mem_map_ptr + (offset - mem_base_addr); +} + + +//------------------------------------------------------------------------------ +// Map in a new EIM page. +//------------------------------------------------------------------------------ +static void _eim_remap_mem(off_t offset) +{ + // unmap old memory page if needed + if (mem_map_ptr != MAP_FAILED) { + if (munmap(mem_map_ptr, mem_page_size) != 0) { + fprintf(stderr, "ERROR: munmap() failed.\n"); + exit(EXIT_FAILURE); + } + } + + // calculate starting address of new page + while (offset % mem_page_size) + offset--; + + // try to map new memory page + mem_map_ptr = mmap(NULL, mem_page_size, PROT_READ | PROT_WRITE, MAP_SHARED, + mem_dev_fd, offset); + if (mem_map_ptr == MAP_FAILED) { + fprintf(stderr, "ERROR: mmap() failed.\n"); + exit(EXIT_FAILURE); + } + + // save last mapped page address + mem_base_addr = offset; +} + + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/sw/novena-eim.h b/sw/novena-eim.h new file mode 100644 index 0000000..75613bf --- /dev/null +++ b/sw/novena-eim.h @@ -0,0 +1,52 @@ +/* + * novena-eim.h + * ------------ + * This module contains the userland magic to set up and use the EIM bus. + * + * + * Author: Pavel Shatov + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define EIM_BASE_ADDR 0x08000000 + +/* Set up EIM bus. + * Returns 0 on success, -1 on failure. + */ +int eim_setup(void); + +/* Write a 32-bit word to EIM. + * If EIM is not set up correctly, this will abort with a bus error. + */ +void eim_write_32(off_t, uint32_t *); + +/* Read a 32-bit word from EIM. + * If EIM is not set up correctly, this will abort with a bus error. + */ +void eim_read_32(off_t, uint32_t *); diff --git a/sw/tc_eim.c b/sw/tc_eim.c new file mode 100644 index 0000000..0461f15 --- /dev/null +++ b/sw/tc_eim.c @@ -0,0 +1,208 @@ +/* + * tc_eim.c + * -------- + * This module contains common code to talk to the FPGA over the EIM bus. + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "novena-eim.h" +#include "cryptech.h" + +static int debug = 0; +static int inited = 0; + +/* ---------------- EIM low-level code ---------------- */ + +static int init(void) +{ + if (inited) + return 0; + + if (eim_setup() != 0) { + fprintf(stderr, "EIM setup failed\n"); + return -1; + } + + inited = 1; + return 0; +} + +/* translate cryptech register number to EIM address + * + * register number format: + * 3 bits segment selector + * 5 bits core selector (6 bits in native eim) + * 8 bits register selector + * + * sss ccccc rrrrrrrr => 00001000000000 sss 0 ccccc rrrrrrrr 00 + */ +static off_t eim_offset(off_t offset) +{ + return EIM_BASE_ADDR + ((offset & ~0x1fff) << 3) + ((offset & 0x1fff) << 2); +} + +/* ---------------- test-case low-level code ---------------- */ + +void tc_set_debug(int onoff) +{ + debug = onoff; +} + +static void dump(char *label, const uint8_t *buf, size_t len) +{ + if (debug) { + int i; + printf("%s [", label); + for (i = 0; i < len; ++i) + printf(" %02x", buf[i]); + printf(" ]\n"); + } +} + +int tc_write(off_t offset, const uint8_t *buf, size_t len) +{ + if (init() != 0) + return -1; + + dump("write ", buf, len); + + offset = eim_offset(offset); + for (; len > 0; offset += 4, buf += 4, len -= 4) { + uint32_t val; + val = htonl(*(uint32_t *)buf); + eim_write_32(offset, &val); + } + + return 0; +} + +int tc_read(off_t offset, uint8_t *buf, size_t len) +{ + uint8_t *rbuf = buf; + int rlen = len; + + if (init() != 0) + return -1; + + offset = eim_offset(offset); + for (; rlen > 0; offset += 4, rbuf += 4, rlen -= 4) { + uint32_t val; + eim_read_32(offset, &val); + *(uint32_t *)rbuf = ntohl(val); + } + + dump("read ", buf, len); + + return 0; +} + +int tc_expected(off_t offset, const uint8_t *expected, size_t len) +{ + uint8_t *buf; + int i; + + buf = malloc(len); + if (buf == NULL) { + perror("malloc"); + return 1; + } + dump("expect", expected, len); + + if (tc_read(offset, buf, len) != 0) + goto errout; + + for (i = 0; i < len; ++i) + if (buf[i] != expected[i]) { + fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", + i, expected[i], buf[i]); + goto errout; + } + + free(buf); + return 0; +errout: + free(buf); + return 1; +} + +int tc_init(off_t offset) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD }; + + return tc_write(offset, buf, 4); +} + +int tc_next(off_t offset) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD }; + + return tc_write(offset, buf, 4); +} + +int tc_wait(off_t offset, uint8_t status, int *count) +{ + uint8_t buf[4]; + int i; + + for (i = 1; ; ++i) { + if (count && (*count > 0) && (i >= *count)) { + fprintf(stderr, "tc_wait timed out\n"); + return 1; + } + if (tc_read(offset, buf, 4) != 0) + return -1; + if (buf[3] & status) { + if (count) + *count = i; + return 0; + } + } +} + +int tc_wait_ready(off_t offset) +{ + int limit = 256; + return tc_wait(offset, STATUS_READY_BIT, &limit); +} + +int tc_wait_valid(off_t offset) +{ + int limit = 256; + return tc_wait(offset, STATUS_VALID_BIT, &limit); +} diff --git a/sw/tc_i2c.c b/sw/tc_i2c.c new file mode 100644 index 0000000..333a531 --- /dev/null +++ b/sw/tc_i2c.c @@ -0,0 +1,335 @@ +/* + * tc_i2c.c + * -------- + * This module contains common code to talk to the FPGA over the I2C bus. + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include "cryptech.h" + +static int debug = 0; +static int i2cfd = -1; + +/* ---------------- I2C low-level code ---------------- */ + +void tc_set_debug(int onoff) +{ + debug = onoff; +} + +static void dump(char *label, const uint8_t *buf, size_t len) +{ + if (debug) { + int i; + printf("%s [", label); + for (i = 0; i < len; ++i) + printf(" %02x", buf[i]); + printf(" ]\n"); + } +} + +static void i2c_close(void) +{ + close(i2cfd); +} + +static int i2c_open(void) +{ + if (i2cfd >= 0) + return 0; + + i2cfd = open(I2C_dev, O_RDWR); + if (i2cfd < 0) { + fprintf(stderr, "Unable to open %s: ", I2C_dev); + perror(""); + i2cfd = 0; + return 1; + } + + if (ioctl(i2cfd, I2C_SLAVE, I2C_addr) < 0) { + fprintf(stderr, "Unable to set I2C slave device 0x%02x: ", I2C_addr); + perror(""); + return 1; + } + + if (atexit(i2c_close) != 0) { + fprintf(stderr, "Unable to set I2C atexit handler."); + return 1; + } + + return 0; +} + +static int i2c_write(const uint8_t *buf, size_t len) +{ + if (i2c_open() != 0) + return 1; + + dump("write ", buf, len); + + if (write(i2cfd, buf, len) != len) { + perror("i2c write failed"); + return 1; + } + + return 0; +} + +static int i2c_read(uint8_t *b) +{ + if (i2c_open() != 0) + return 1; + + /* read() on the i2c device only returns one byte at a time, + * and tc_get_resp() needs to parse the response one byte at a time + */ + if (read(i2cfd, b, 1) != 1) { + perror("i2c read failed"); + return 1; + } + + return 0; +} + +/* ---------------- test-case low-level code ---------------- */ + +/* coretest command codes */ +#define SOC 0x55 +#define EOC 0xaa +#define READ_CMD 0x10 +#define WRITE_CMD 0x11 +#define RESET_CMD 0x01 + +/* coretest response codes */ +#define SOR 0xaa +#define EOR 0x55 +#define READ_OK 0x7f +#define WRITE_OK 0x7e +#define RESET_OK 0x7d +#define UNKNOWN 0xfe +#define ERROR 0xfd + +static int tc_send_write_cmd(off_t offset, const uint8_t *data) +{ + uint8_t buf[9] = { SOC, WRITE_CMD, (offset >> 8) & 0xff, offset & 0xff, + data[0], data[1], data[2], data[3], EOC }; + + return i2c_write(buf, sizeof(buf)); +} + +static int tc_send_read_cmd(off_t offset) +{ + uint8_t buf[5] = { SOC, READ_CMD, (offset >> 8) & 0xff, offset & 0xff, EOC }; + + return i2c_write(buf, sizeof(buf)); +} + +static int tc_get_resp(uint8_t *buf, size_t len) +{ + int i; + + for (i = 0; i < len; ++i) { + if (i2c_read(&buf[i]) != 0) + return 1; + if ((i == 0) && (buf[i] != SOR)) { + /* we've gotten out of sync, and there's probably nothing we can do */ + fprintf(stderr, "response byte 0: expected 0x%02x (SOR), got 0x%02x\n", + SOR, buf[0]); + return 1; + } + else if (i == 1) { /* response code */ + switch (buf[i]) { + case READ_OK: + len = 9; + break; + case WRITE_OK: + len = 5; + break; + case RESET_OK: + len = 3; + break; + case ERROR: + case UNKNOWN: + len = 4; + break; + default: + /* we've gotten out of sync, and there's probably nothing we can do */ + fprintf(stderr, "unknown response code 0x%02x\n", buf[i]); + return 1; + } + } + } + + dump("read ", buf, len); + + return 0; +} + +static int tc_compare(uint8_t *buf, const uint8_t *expected, size_t len) +{ + int i; + + /* start at byte 1 because SOR has already been tested */ + for (i = 1; i < len; ++i) { + if (buf[i] != expected[i]) { + fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", + i, expected[i], buf[i]); + return 1; + } + } + + return 0; +} + +static int tc_get_write_resp(off_t offset) +{ + uint8_t buf[5]; + uint8_t expected[5] = { SOR, WRITE_OK, (offset >> 8) & 0xff, offset & 0xff, EOR }; + + return + tc_get_resp(buf, sizeof(buf)) || + tc_compare(buf, expected, sizeof(expected)); +} + +static int tc_get_read_resp(off_t offset, uint8_t *data) +{ + uint8_t buf[9]; + uint8_t expected[4] = { SOR, READ_OK, (offset >> 8) & 0xff, offset & 0xff }; + + if ((tc_get_resp(buf, sizeof(buf)) != 0) || + (tc_compare(buf, expected, 4) != 0) || buf[8] != EOR) + return 1; + + data[0] = buf[4]; + data[1] = buf[5]; + data[2] = buf[6]; + data[3] = buf[7]; + + return 0; +} + +static int tc_get_read_resp_expected(off_t offset, const uint8_t *data) +{ + uint8_t buf[9]; + uint8_t expected[9] = { SOR, READ_OK, (offset >> 8) & 0xff, offset & 0xff, + data[0], data[1], data[2], data[3], EOR }; + + dump("expect", expected, 9); + + return (tc_get_resp(buf, sizeof(buf)) || + tc_compare(buf, expected, sizeof(buf))); +} + +int tc_write(off_t offset, const uint8_t *buf, size_t len) +{ + for (; len > 0; offset++, buf += 4, len -= 4) { + if (tc_send_write_cmd(offset, buf) || + tc_get_write_resp(offset)) + return 1; + } + + return 0; +} + +int tc_read(off_t offset, uint8_t *buf, size_t len) +{ + for (; len > 0; offset++, buf += 4, len -= 4) { + if (tc_send_read_cmd(offset) || + tc_get_read_resp(offset, buf)) + return 1; + } + + return 0; +} + +int tc_expected(off_t offset, const uint8_t *buf, size_t len) +{ + for (; len > 0; offset++, buf += 4, len -= 4) { + if (tc_send_read_cmd(offset) || + tc_get_read_resp_expected(offset, buf)) + return 1; + } + + return 0; +} + +int tc_init(off_t offset) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD }; + + return tc_write(offset, buf, 4); +} + +int tc_next(off_t offset) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD }; + + return tc_write(offset, buf, 4); +} + +int tc_wait(off_t offset, uint8_t status, int *count) +{ + uint8_t buf[4]; + int i; + + for (i = 1; ; ++i) { + if (count && (*count > 0) && (i >= *count)) { + fprintf(stderr, "tc_wait timed out\n"); + return 1; + } + if (tc_read(offset, buf, 4) != 0) + return -1; + if (buf[3] & status) { + if (count) + *count = i; + return 0; + } + } +} + +int tc_wait_ready(off_t offset) +{ + int limit = 10; + return tc_wait(offset, STATUS_READY_BIT, &limit); +} + +int tc_wait_valid(off_t offset) +{ + int limit = 10; + return tc_wait(offset, STATUS_VALID_BIT, &limit); +} diff --git a/sw/trng_extractor.c b/sw/trng_extractor.c new file mode 100644 index 0000000..f71a5d6 --- /dev/null +++ b/sw/trng_extractor.c @@ -0,0 +1,158 @@ +/* + * trng_extractor.c + * ---------------- + * This program extracts raw data from the avalanche_entropy, rosc_entropy, + * and csprng cores. + * + * Author: Paul Selkirk + * Copyright (c) 2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "cryptech.h" + +char *usage = +"%s [-a|r|c] [-n #] [-o file]\n\ +\n\ +-a avalanche entropy\n\ +-r rosc entropy\n\ +-c csprng (default data source)\n\ +-n number of 4-byte samples (scale with K, M, or G suffix)\n\ +-o output file (defaults to stdout)\n\ +"; + +/* extract one data sample */ +static int extract(off_t status_addr, off_t data_addr, uint32_t *data) +{ + if (tc_wait(status_addr, ENTROPY1_STATUS_VALID, NULL) != 0) { + fprintf(stderr, "tc_wait failed\n"); + return 1; + } + + if (tc_read(data_addr, (uint8_t *)data, 4) != 0) { + fprintf(stderr, "tc_read failed\n"); + return 1; + } + + return 0; +} + +/* main */ +int main(int argc, char *argv[]) +{ + int i, opt; + unsigned long num_words = 1; + char *endptr; + off_t status_addr = CSPRNG_ADDR_STATUS; + off_t data_addr = CSPRNG_ADDR_RANDOM; + FILE *output = stdout; + uint32_t data; + + /* parse command line */ + while ((opt = getopt(argc, argv, "h?arcn:o:")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'a': + status_addr = ENTROPY1_ADDR_STATUS; + data_addr = ENTROPY1_ADDR_ENTROPY; + break; + case 'r': + status_addr = ENTROPY2_ADDR_STATUS; + data_addr = ENTROPY2_ADDR_ENTROPY; + break; + case 'c': + status_addr = CSPRNG_ADDR_STATUS; + data_addr = CSPRNG_ADDR_RANDOM; + break; + case 'n': + num_words = strtoul(optarg, &endptr, 10); + switch (toupper(*endptr)) { + case '\0': + break; + case 'K': + num_words *= 1000; + break; + case 'M': + num_words *= 1000000; + break; + case 'G': + num_words *= 1000000000; + break; + default: + fprintf(stderr, "unsupported -n suffix %s\n", endptr); + return EXIT_FAILURE; + } + break; + case 'o': + output = fopen(optarg, "wb+"); + if (output == NULL) { + fprintf(stderr, "error opening output file %s: ", optarg); + perror(""); + return EXIT_FAILURE; + } + break; + default: + errout: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + if (optind < argc) { + fprintf(stderr, "%s: invalid argument%s --", + argv[0], argc - optind > 1 ? "s" : ""); + do { + fprintf(stderr, " %s", argv[optind]); + ++optind; + } while (optind < argc); + fprintf(stderr, "\n"); + goto errout; + } + + /* get the data */ + for (i = 0; i < num_words; ++i) { + if (extract(status_addr, data_addr, &data) != 0) + return EXIT_FAILURE; + if (fwrite(&data, sizeof(data), 1, output) != 1) { + perror("fwrite"); + fclose(output); + return EXIT_FAILURE; + } + } + + fclose(output); + return EXIT_SUCCESS; +} diff --git a/sw/trng_tester.c b/sw/trng_tester.c new file mode 100644 index 0000000..f0b80d0 --- /dev/null +++ b/sw/trng_tester.c @@ -0,0 +1,371 @@ +/* + * trng_tester.c + * -------------- + * This program sends several commands to the TRNG subsystem + * in order to verify the avalanche_entropy, rosc_entropy, and csprng cores. + * + * Note: This version of the program talks to the FPGA over an EIM bus. + * + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cryptech.h" + +char *usage = "Usage: %s [-h] [-d] [-q] [-r] [-w] [-n #] tc...\n"; + +int debug = 0; +int quiet = 0; +int repeat = 0; +int num_words = 10; +int wait_stats = 0; + +/* ---------------- sanity test case ---------------- */ + +int TC0() +{ + uint8_t board_name0[4] = "PVT1"; + uint8_t board_name1[4] = " "; + uint8_t board_version[4] = "0.10"; + + uint8_t comm_name0[4] = "eim "; + uint8_t comm_name1[4] = " "; + uint8_t comm_version[4] = "0.10"; + + uint8_t t[4]; + + if (!quiet) + printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); + + /* write current time into dummy register, then try to read it back + * to make sure that we can actually write something into EIM + */ + (void)time((time_t *)t); + if (tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4) != 0) + return 1; + + if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || + tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || + tc_expected(BOARD_ADDR_VERSION, board_version, 4) || + tc_expected(BOARD_ADDR_DUMMY, (void *)t, 4)) + return 1; + + if (!quiet) + printf("TC0-2: Reading name and version words from communications core.\n"); + + return + tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || + tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || + tc_expected(COMM_ADDR_VERSION, comm_version, 4); +} + +/* ---------------- trng test cases ---------------- */ + +/* TC1: Read name and version from trng core. */ +int TC1(void) +{ + uint8_t name0[4] = "trng"; + uint8_t name1[4] = " "; + uint8_t version[4] = "0.01"; + + if (!quiet) + printf("TC1: Reading name and version words from trng core.\n"); + + return + tc_expected(TRNG_ADDR_NAME0, name0, 4) || + tc_expected(TRNG_ADDR_NAME1, name1, 4) || + tc_expected(TRNG_ADDR_VERSION, version, 4); +} + +/* XXX test cases for setting blinkenlights? */ +/* XXX set 'discard' control bit, see if we read the same value */ + +/* ---------------- avalanche_entropy test cases ---------------- */ + +/* TC2: Read name and version from avalanche_entropy core. */ +int TC2(void) +{ + uint8_t name0[4] = "extn"; + uint8_t name1[4] = "oise"; + uint8_t version[4] = "0.10"; + + if (!quiet) + printf("TC2: Reading name and version words from avalanche_entropy core.\n"); + + return + tc_expected(ENTROPY1_ADDR_NAME0, name0, 4) || + tc_expected(ENTROPY1_ADDR_NAME1, name1, 4) || + tc_expected(ENTROPY1_ADDR_VERSION, version, 4); +} + +/* XXX clear 'enable' control bit, see if we read the same value */ + +/* TC3: Read random data from avalanche_entropy. */ +int TC3(void) +{ + int i, n; + uint32_t entropy; + + if (!quiet) + printf("TC3: Read random data from avalanche_entropy.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 0; + if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID, &n) != 0) + return 1; + /* read entropy data */ + if (tc_read(ENTROPY1_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) + return 1; + /* display entropy data */ + if (!debug) { + if (wait_stats) + printf("%08x %d\n", entropy, n); + else + printf("%08x\n", entropy); + } + } + + return 0; +} + +/* ---------------- rosc_entropy test cases ---------------- */ + +/* TC4: Read name and version from rosc_entropy core. */ +int TC4(void) +{ + uint8_t name0[4] = "rosc"; + uint8_t name1[4] = " ent"; + uint8_t version[4] = "0.10"; + + if (!quiet) + printf("TC4: Reading name and version words from rosc_entropy core.\n"); + + return + tc_expected(ENTROPY2_ADDR_NAME0, name0, 4) || + tc_expected(ENTROPY2_ADDR_NAME1, name1, 4) || + tc_expected(ENTROPY2_ADDR_VERSION, version, 4); +} + +/* XXX clear 'enable' control bit, see if we read the same value */ + +/* TC5: Read random data from rosc_entropy. */ +int TC5(void) +{ + int i, n; + uint32_t entropy; + + if (!quiet) + printf("TC5: Read random data from rosc_entropy.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 0; + if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID, &n) != 0) + return 1; + /* read entropy data */ + if (tc_read(ENTROPY2_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) + return 1; + /* display entropy data */ + if (!debug) { + if (wait_stats) + printf("%08x %d\n", entropy, n); + else + printf("%08x\n", entropy); + } + } + + return 0; +} + +/* ---------------- trng_csprng test cases ---------------- */ + +/* TC6: Read name and version from trng_csprng core. */ +int TC6(void) +{ + /* XXX csprng core currently doesn't have name/version registers */ + return 0; +} + +/* XXX clear 'enable' control bit, see if we read the same value */ +/* XXX set 'seed' control bit, see if we read the same value */ + +/* TC7: Read random data from trng_csprng. */ +int TC7(void) +{ + int i, n; + uint32_t random; + + if (!quiet) + printf("TC7: Read random data from trng_csprng.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 0; + if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID, &n) != 0) + return 1; + /* read random data */ + if (tc_read(CSPRNG_ADDR_RANDOM, (uint8_t *)&random, 4) != 0) + return 1; + /* display random data */ + if (!debug) { + if (wait_stats) + printf("%08x %d\n", random, n); + else + printf("%08x\n", random); + } + } + + return 0; +} + + +/* ---------------- main ---------------- */ + +/* signal handler for ctrl-c to end repeat testing */ +unsigned long iter = 0; +struct timeval tv_start, tv_end; +void sighandler(int unused) +{ + double tv_diff; + + gettimeofday(&tv_end, NULL); + tv_diff = (double)(tv_end.tv_sec - tv_start.tv_sec) + + (double)(tv_end.tv_usec - tv_start.tv_usec)/1000000; + printf("\n%lu iterations in %.3f seconds (%.3f iterations/sec)\n", + iter, tv_diff, (double)iter/tv_diff); + exit(EXIT_SUCCESS); +} + +int main(int argc, char *argv[]) +{ + typedef int (*tcfp)(void); + tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 }; + int i, j, opt; + + while ((opt = getopt(argc, argv, "h?dqrn:w")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + tc_set_debug(1); + debug = 1; + break; + case 'q': + quiet = 1; + break; + case 'r': + repeat = 1; + break; + case 'n': + num_words = atoi(optarg); + if (num_words <= 0) { + fprintf(stderr, "-n requires a positive integer argument\n"); + return EXIT_FAILURE; + } + break; + case 'w': + wait_stats = 1; + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + /* repeat one test until interrupted */ + if (repeat) { + tcfp tc; + if (optind != argc - 1) { + fprintf(stderr, "only one test case can be repeated\n"); + return EXIT_FAILURE; + } + j = atoi(argv[optind]); + if (j < 0 || j >= sizeof(all_tests)/sizeof(all_tests[0])) { + fprintf(stderr, "invalid test number %s\n", argv[optind]); + return EXIT_FAILURE; + } + tc = (all_tests[j]); + srand(time(NULL)); + signal(SIGINT, sighandler); + gettimeofday(&tv_start, NULL); + while (1) { + ++iter; + if ((iter & 0xffff) == 0) { + printf("."); + fflush(stdout); + } + if (tc() != 0) + sighandler(0); + } + return EXIT_SUCCESS; /*NOTREACHED*/ + } + + /* no args == run all tests */ + if (optind >= argc) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + return EXIT_SUCCESS; + } + + /* run one or more tests (by number) or groups of tests (by name) */ + for (i = optind; i < argc; ++i) { + if (strcmp(argv[i], "all") == 0) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (isdigit(argv[i][0]) && + (((j = atoi(argv[i])) >= 0) && + (j < sizeof(all_tests)/sizeof(all_tests[0])))) { + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else { + fprintf(stderr, "unknown test case %s\n", argv[i]); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} -- cgit v1.2.3 From d07c710e9a82c46e20bc8262308117edf7a0ca11 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Wed, 22 Apr 2015 01:39:12 -0400 Subject: Make position-independent libraries for cryptlib. --- sw/Makefile | 2 +- sw/Makefile.i2c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sw/Makefile b/sw/Makefile index 93976d7..0dbd61a 100755 --- a/sw/Makefile +++ b/sw/Makefile @@ -1,5 +1,5 @@ CC = gcc -CFLAGS = -Wall +CFLAGS = -Wall -fPIC LIB = libcryptech.a BIN = hash hash_tester trng_extractor trng_tester diff --git a/sw/Makefile.i2c b/sw/Makefile.i2c index fa136a4..98cd541 100755 --- a/sw/Makefile.i2c +++ b/sw/Makefile.i2c @@ -1,5 +1,5 @@ CC = gcc -CFLAGS = -Wall +CFLAGS = -Wall -fPIC LIB = libcryptech_i2c.a BIN = hash_i2c hash_tester_i2c trng_extractor_i2c trng_tester_i2c -- cgit v1.2.3