From 0f12a4d79d85bc8cf9c32d41e31d229dc7e847d9 Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Tue, 17 Jan 2017 23:51:08 -0500
Subject: Track changes to the core_selector generator.

---
 eim/build/Makefile | 12 ++++++------
 fmc/build/Makefile | 11 ++++++-----
 i2c/build/Makefile | 11 ++++++-----
 3 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/eim/build/Makefile b/eim/build/Makefile
index 8b984a2..a6b6d33 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -17,32 +17,32 @@ top_module	= novena_top
 isedir		= /opt/Xilinx/14.7/ISE_DS
 xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
 ucf		?= ../ucf/$(project).ucf
-#ucf		?= ../ucf/$(project)-dev_bridge_board.ucf
 
 all:	$(project).bit
 
 # Build the default core_selector if it doesn't already exist.
 
 CONFIG          = $(CORE_TREE)/platform/common/config
+CONFIG_GEN      = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b novena
 core_selector.v core_vfiles.mk:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg
+	$(CONFIG_GEN) -p rsa
 
 # Build some different configurations
 
 bare:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
+	$(CONFIG_GEN) -p bare
 	$(MAKE) project=$(project)_bare ucf=$(ucf)
 
 trng:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
+	$(CONFIG_GEN) -p trng
 	$(MAKE) project=$(project)_trng ucf=$(ucf)
 
 hash:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
+	$(CONFIG_GEN) -p hash
 	$(MAKE) project=$(project)_hash ucf=$(ucf)
 
 rsa:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
+	$(CONFIG_GEN) -p rsa
 	$(MAKE) project=$(project)_rsa ucf=$(ucf)
 
 # Verilog files that always go with builds on this platform.
diff --git a/fmc/build/Makefile b/fmc/build/Makefile
index c317d02..24d5951 100644
--- a/fmc/build/Makefile
+++ b/fmc/build/Makefile
@@ -23,25 +23,26 @@ all:	$(project).bit
 # Build the default core_selector if it doesn't already exist.
 
 CONFIG          = $(CORE_TREE)/platform/common/config
+CONFIG_GEN      = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b dev-bridge
 core_selector.v core_vfiles.mk:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg
+	$(CONFIG_GEN) -p rsa
 
 # Build some different configurations
 
 bare:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
+	$(CONFIG_GEN) -p bare
 	$(MAKE) project=$(project)_bare ucf=$(ucf)
 
 trng:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
+	$(CONFIG_GEN) -p trng
 	$(MAKE) project=$(project)_trng ucf=$(ucf)
 
 hash:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
+	$(CONFIG_GEN) -p hash
 	$(MAKE) project=$(project)_hash ucf=$(ucf)
 
 rsa:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
+	$(CONFIG_GEN) -p rsa
 	$(MAKE) project=$(project)_rsa ucf=$(ucf)
 
 # Verilog files that always go with builds on this platform.
diff --git a/i2c/build/Makefile b/i2c/build/Makefile
index dc020c8..a890242 100644
--- a/i2c/build/Makefile
+++ b/i2c/build/Makefile
@@ -23,25 +23,26 @@ all:	$(project).bit
 # Build the default core_selector if it doesn't already exist.
 
 CONFIG          = $(CORE_TREE)/platform/common/config
+CONFIG_GEN      = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b novena
 core_selector.v core_vfiles.mk:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg
+	$(CONFIG_GEN) -p rsa
 
 # Build some different configurations
 
 bare:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
+	$(CONFIG_GEN) -p bare
 	$(MAKE) project=$(project)_bare ucf=$(ucf)
 
 trng:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
+	$(CONFIG_GEN) -p trng
 	$(MAKE) project=$(project)_trng ucf=$(ucf)
 
 hash:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
+	$(CONFIG_GEN) -p hash
 	$(MAKE) project=$(project)_hash ucf=$(ucf)
 
 rsa:
-	$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
+	$(CONFIG_GEN) -p rsa
 	$(MAKE) project=$(project)_rsa ucf=$(ucf)
 
 # Verilog files that always go with builds on this platform.
-- 
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