diff options
Diffstat (limited to 'sw/cryptech.h')
| -rw-r--r-- | sw/cryptech.h | 405 |
1 files changed, 197 insertions, 208 deletions
diff --git a/sw/cryptech.h b/sw/cryptech.h index 13088b1..8fbef62 100644 --- a/sw/cryptech.h +++ b/sw/cryptech.h @@ -70,17 +70,6 @@ in order to map it into a 16-bit address space. // Default sizes //------------------------------------------------------------------ #define CORE_SIZE 0x100 -#define SEGMENT_SIZE 0x20 * CORE_SIZE - - -//------------------------------------------------------------------ -// Segments -//------------------------------------------------------------------ -#define SEGMENT_OFFSET_GLOBALS 0 * SEGMENT_SIZE -#define SEGMENT_OFFSET_HASHES 1 * SEGMENT_SIZE -#define SEGMENT_OFFSET_RNGS 2 * SEGMENT_SIZE -#define SEGMENT_OFFSET_CIPHERS 3 * SEGMENT_SIZE -#define SEGMENT_OFFSET_MATH 4 * SEGMENT_SIZE //------------------------------------------------------------------ @@ -104,19 +93,16 @@ in order to map it into a 16-bit address space. //------------------------------------------------------------------ -// Board segment. // Board-level registers and communication channel registers //------------------------------------------------------------------ -#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0 * CORE_SIZE) -#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 -#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 -#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION -#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + 0xFF +#define BOARD_ADDR_NAME0 ADDR_NAME0 +#define BOARD_ADDR_NAME1 ADDR_NAME1 +#define BOARD_ADDR_VERSION ADDR_VERSION +#define BOARD_ADDR_DUMMY 0xFF -#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (1 * CORE_SIZE) -#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 -#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 -#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION +#define COMM_ADDR_NAME0 ADDR_NAME0 +#define COMM_ADDR_NAME1 ADDR_NAME1 +#define COMM_ADDR_VERSION ADDR_VERSION // current name and version values #define NOVENA_BOARD_NAME0 "PVT1" @@ -133,45 +119,42 @@ in order to map it into a 16-bit address space. //------------------------------------------------------------------ -// Hashes segment. +// Hash cores //------------------------------------------------------------------ // addresses common to all hash cores #define ADDR_BLOCK 0x10 #define ADDR_DIGEST 0x20 // except SHA512 -// addresses and codes for the specific hash cores. -#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0 * CORE_SIZE) -#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 -#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 -#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION -#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL -#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS -#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK -#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST +// SHA-1 core +#define SHA1_ADDR_NAME0 ADDR_NAME0 +#define SHA1_ADDR_NAME1 ADDR_NAME1 +#define SHA1_ADDR_VERSION ADDR_VERSION +#define SHA1_ADDR_CTRL ADDR_CTRL +#define SHA1_ADDR_STATUS ADDR_STATUS +#define SHA1_ADDR_BLOCK ADDR_BLOCK +#define SHA1_ADDR_DIGEST ADDR_DIGEST #define SHA1_BLOCK_LEN bitsToBytes(512) #define SHA1_LENGTH_LEN bitsToBytes(64) #define SHA1_DIGEST_LEN bitsToBytes(160) -#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1 * CORE_SIZE) -#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 -#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 -#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION -#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL -#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS -#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK -#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST +#define SHA256_ADDR_NAME0 ADDR_NAME0 +#define SHA256_ADDR_NAME1 ADDR_NAME1 +#define SHA256_ADDR_VERSION ADDR_VERSION +#define SHA256_ADDR_CTRL ADDR_CTRL +#define SHA256_ADDR_STATUS ADDR_STATUS +#define SHA256_ADDR_BLOCK ADDR_BLOCK +#define SHA256_ADDR_DIGEST ADDR_DIGEST #define SHA256_BLOCK_LEN bitsToBytes(512) #define SHA256_LENGTH_LEN bitsToBytes(64) #define SHA256_DIGEST_LEN bitsToBytes(256) -#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2 * CORE_SIZE) -#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 -#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 -#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION -#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL -#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS -#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK -#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + 0x40 +#define SHA512_ADDR_NAME0 ADDR_NAME0 +#define SHA512_ADDR_NAME1 ADDR_NAME1 +#define SHA512_ADDR_VERSION ADDR_VERSION +#define SHA512_ADDR_CTRL ADDR_CTRL +#define SHA512_ADDR_STATUS ADDR_STATUS +#define SHA512_ADDR_BLOCK ADDR_BLOCK +#define SHA512_ADDR_DIGEST 0x40 #define SHA512_BLOCK_LEN bitsToBytes(1024) #define SHA512_LENGTH_LEN bitsToBytes(128) #define SHA512_224_DIGEST_LEN bitsToBytes(224) @@ -198,69 +181,64 @@ in order to map it into a 16-bit address space. //----------------------------------------------------------------- -// TRNG segment. +// TRNG cores //----------------------------------------------------------------- // addresses and codes for the TRNG cores */ -#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x00 * CORE_SIZE) -#define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 -#define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 -#define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION -#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + 0x10 +#define TRNG_ADDR_NAME0 ADDR_NAME0 +#define TRNG_ADDR_NAME1 ADDR_NAME1 +#define TRNG_ADDR_VERSION ADDR_VERSION +#define TRNG_ADDR_CTRL 0x10 #define TRNG_CTRL_DISCARD 1 #define TRNG_CTRL_TEST_MODE 2 -#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + 0x11 +#define TRNG_ADDR_STATUS 0x11 // no status bits defined (yet) -#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + 0x13 +#define TRNG_ADDR_DELAY 0x13 -#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x05 * CORE_SIZE) -#define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 -#define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 -#define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION -#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + 0x10 +#define ENTROPY1_ADDR_NAME0 ADDR_NAME0 +#define ENTROPY1_ADDR_NAME1 ADDR_NAME1 +#define ENTROPY1_ADDR_VERSION ADDR_VERSION +#define ENTROPY1_ADDR_CTRL 0x10 #define ENTROPY1_CTRL_ENABLE 1 -#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + 0x11 +#define ENTROPY1_ADDR_STATUS 0x11 #define ENTROPY1_STATUS_VALID 1 -#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + 0x20 -#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + 0x30 - -#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x06 * CORE_SIZE) -#define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 -#define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 -#define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION -#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + 0x10 +#define ENTROPY1_ADDR_ENTROPY 0x20 +#define ENTROPY1_ADDR_DELTA 0x30 + +#define ENTROPY2_ADDR_NAME0 ADDR_NAME0 +#define ENTROPY2_ADDR_NAME1 ADDR_NAME1 +#define ENTROPY2_ADDR_VERSION ADDR_VERSION +#define ENTROPY2_ADDR_CTRL 0x10 #define ENTROPY2_CTRL_ENABLE 1 -#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + 0x11 +#define ENTROPY2_ADDR_STATUS 0x11 #define ENTROPY2_STATUS_VALID 1 -#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + 0x18 -#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + 0x19 -#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + 0x20 -#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + 0x21 -#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + 0x22 - -#define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * CORE_SIZE) -#define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 -#define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 -#define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION -#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + 0x10 +#define ENTROPY2_ADDR_OPA 0x18 +#define ENTROPY2_ADDR_OPB 0x19 +#define ENTROPY2_ADDR_ENTROPY 0x20 +#define ENTROPY2_ADDR_RAW 0x21 +#define ENTROPY2_ADDR_ROSC 0x22 + +#define MIXER_ADDR_NAME0 ADDR_NAME0 +#define MIXER_ADDR_NAME1 ADDR_NAME1 +#define MIXER_ADDR_VERSION ADDR_VERSION +#define MIXER_ADDR_CTRL 0x10 #define MIXER_CTRL_ENABLE 1 #define MIXER_CTRL_RESTART 2 -#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + 0x11 +#define MIXER_ADDR_STATUS 0x11 // no status bits defined (yet) -#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + 0x20 +#define MIXER_ADDR_TIMEOUT 0x20 -#define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * CORE_SIZE) -#define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 -#define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 -#define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION -#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + 0x10 +#define CSPRNG_ADDR_NAME0 ADDR_NAME0 +#define CSPRNG_ADDR_NAME1 ADDR_NAME1 +#define CSPRNG_ADDR_VERSION ADDR_VERSION +#define CSPRNG_ADDR_CTRL 0x10 #define CSPRNG_CTRL_ENABLE 1 #define CSPRNG_CTRL_SEED 2 -#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + 0x11 +#define CSPRNG_ADDR_STATUS 0x11 #define CSPRNG_STATUS_VALID 1 -#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + 0x20 -#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + 0x40 -#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + 0x41 -#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + 0x42 +#define CSPRNG_ADDR_RANDOM 0x20 +#define CSPRNG_ADDR_NROUNDS 0x40 +#define CSPRNG_ADDR_NBLOCKS_LO 0x41 +#define CSPRNG_ADDR_NBLOCKS_HI 0x42 // current name and version values #define TRNG_NAME0 "trng" @@ -275,44 +253,47 @@ in order to map it into a 16-bit address space. #define ROSC_ENTROPY_NAME1 " ent" #define ROSC_ENTROPY_VERSION "0.10" +#define MIXER_NAME0 "rngm" +#define MIXER_NAME1 "ixer" +#define MIXER_VERSION "0.50" + #define CSPRNG_NAME0 "cspr" #define CSPRNG_NAME1 "ng " #define CSPRNG_VERSION "0.50" // ----------------------------------------------------------------- -// CIPHERS segment. +// Cipher cores // ----------------------------------------------------------------- -// aes core. -#define AES_ADDR_BASE SEGMENT_OFFSET_CIPHERS + (0 * CORE_SIZE) -#define AES_ADDR_NAME0 AES_ADDR_BASE + ADDR_NAME0 -#define AES_ADDR_NAME1 AES_ADDR_BASE + ADDR_NAME1 -#define AES_ADDR_VERSION AES_ADDR_BASE + ADDR_VERSION -#define AES_ADDR_CTRL AES_ADDR_BASE + ADDR_CTRL -#define AES_ADDR_STATUS AES_ADDR_BASE + ADDR_STATUS - -#define AES_ADDR_CONFIG AES_ADDR_BASE + 0x0a +// AES core +#define AES_ADDR_NAME0 ADDR_NAME0 +#define AES_ADDR_NAME1 ADDR_NAME1 +#define AES_ADDR_VERSION ADDR_VERSION +#define AES_ADDR_CTRL ADDR_CTRL +#define AES_ADDR_STATUS ADDR_STATUS + +#define AES_ADDR_CONFIG 0x0a #define AES_CONFIG_ENCDEC 1 #define AES_CONFIG_KEYLEN 2 -#define AES_ADDR_KEY0 AES_ADDR_BASE + 0x10 -#define AES_ADDR_KEY1 AES_ADDR_BASE + 0x11 -#define AES_ADDR_KEY2 AES_ADDR_BASE + 0x12 -#define AES_ADDR_KEY3 AES_ADDR_BASE + 0x13 -#define AES_ADDR_KEY4 AES_ADDR_BASE + 0x14 -#define AES_ADDR_KEY5 AES_ADDR_BASE + 0x15 -#define AES_ADDR_KEY6 AES_ADDR_BASE + 0x16 -#define AES_ADDR_KEY7 AES_ADDR_BASE + 0x17 - -#define AES_ADDR_BLOCK0 AES_ADDR_BASE + 0x20 -#define AES_ADDR_BLOCK1 AES_ADDR_BASE + 0x21 -#define AES_ADDR_BLOCK2 AES_ADDR_BASE + 0x22 -#define AES_ADDR_BLOCK3 AES_ADDR_BASE + 0x23 - -#define AES_ADDR_RESULT0 AES_ADDR_BASE + 0x30 -#define AES_ADDR_RESULT1 AES_ADDR_BASE + 0x31 -#define AES_ADDR_RESULT2 AES_ADDR_BASE + 0x32 -#define AES_ADDR_RESULT3 AES_ADDR_BASE + 0x33 +#define AES_ADDR_KEY0 0x10 +#define AES_ADDR_KEY1 0x11 +#define AES_ADDR_KEY2 0x12 +#define AES_ADDR_KEY3 0x13 +#define AES_ADDR_KEY4 0x14 +#define AES_ADDR_KEY5 0x15 +#define AES_ADDR_KEY6 0x16 +#define AES_ADDR_KEY7 0x17 + +#define AES_ADDR_BLOCK0 0x20 +#define AES_ADDR_BLOCK1 0x21 +#define AES_ADDR_BLOCK2 0x22 +#define AES_ADDR_BLOCK3 0x23 + +#define AES_ADDR_RESULT0 0x30 +#define AES_ADDR_RESULT1 0x31 +#define AES_ADDR_RESULT2 0x32 +#define AES_ADDR_RESULT3 0x33 // current name and version values #define AES_CORE_NAME0 "aes " @@ -321,63 +302,62 @@ in order to map it into a 16-bit address space. // Chacha core -#define CHACHA_ADDR_BASE SEGMENT_OFFSET_CIPHERS + (1 * CORE_SIZE) -#define CHACHA_ADDR_NAME0 CHACHA_ADDR_BASE + ADDR_NAME0 -#define CHACHA_ADDR_NAME1 CHACHA_ADDR_BASE + ADDR_NAME1 -#define CHACHA_ADDR_VERSION CHACHA_ADDR_BASE + ADDR_VERSION -#define CHACHA_ADDR_CTRL CHACHA_ADDR_BASE + ADDR_CTRL -#define CHACHA_ADDR_STATUS CHACHA_ADDR_BASE + ADDR_STATUS - -#define CHACHA_ADDR_KEYLEN CHACHA_ADDR_BASE + 0x0a +#define CHACHA_ADDR_NAME0 ADDR_NAME0 +#define CHACHA_ADDR_NAME1 ADDR_NAME1 +#define CHACHA_ADDR_VERSION ADDR_VERSION +#define CHACHA_ADDR_CTRL ADDR_CTRL +#define CHACHA_ADDR_STATUS ADDR_STATUS + +#define CHACHA_ADDR_KEYLEN 0x0a #define CHACHA_KEYLEN 1 -#define CHACHA_ADDR_ROUNDS CHACHA_ADDR_BASE + 0x0b - -#define CHACHA_ADDR_KEY0 CHACHA_ADDR_BASE + 0x10 -#define CHACHA_ADDR_KEY1 CHACHA_ADDR_BASE + 0x11 -#define CHACHA_ADDR_KEY2 CHACHA_ADDR_BASE + 0x12 -#define CHACHA_ADDR_KEY3 CHACHA_ADDR_BASE + 0x13 -#define CHACHA_ADDR_KEY4 CHACHA_ADDR_BASE + 0x14 -#define CHACHA_ADDR_KEY5 CHACHA_ADDR_BASE + 0x15 -#define CHACHA_ADDR_KEY6 CHACHA_ADDR_BASE + 0x16 -#define CHACHA_ADDR_KEY7 CHACHA_ADDR_BASE + 0x17 - -#define CHACHA_ADDR_IV0 CHACHA_ADDR_BASE + 0x20 -#define CHACHA_ADDR_IV1 CHACHA_ADDR_BASE + 0x21 - -#define CHACHA_ADDR_DATA_IN0 CHACHA_ADDR_BASE + 0x40 -#define CHACHA_ADDR_DATA_IN1 CHACHA_ADDR_BASE + 0x41 -#define CHACHA_ADDR_DATA_IN2 CHACHA_ADDR_BASE + 0x42 -#define CHACHA_ADDR_DATA_IN3 CHACHA_ADDR_BASE + 0x43 -#define CHACHA_ADDR_DATA_IN4 CHACHA_ADDR_BASE + 0x44 -#define CHACHA_ADDR_DATA_IN5 CHACHA_ADDR_BASE + 0x45 -#define CHACHA_ADDR_DATA_IN6 CHACHA_ADDR_BASE + 0x46 -#define CHACHA_ADDR_DATA_IN7 CHACHA_ADDR_BASE + 0x47 -#define CHACHA_ADDR_DATA_IN8 CHACHA_ADDR_BASE + 0x48 -#define CHACHA_ADDR_DATA_IN9 CHACHA_ADDR_BASE + 0x49 -#define CHACHA_ADDR_DATA_IN10 CHACHA_ADDR_BASE + 0x4a -#define CHACHA_ADDR_DATA_IN11 CHACHA_ADDR_BASE + 0x4b -#define CHACHA_ADDR_DATA_IN12 CHACHA_ADDR_BASE + 0x4c -#define CHACHA_ADDR_DATA_IN13 CHACHA_ADDR_BASE + 0x4d -#define CHACHA_ADDR_DATA_IN14 CHACHA_ADDR_BASE + 0x4e -#define CHACHA_ADDR_DATA_IN15 CHACHA_ADDR_BASE + 0x4f - -#define CHACHA_ADDR_DATA_OUT0 CHACHA_ADDR_BASE + 0x80 -#define CHACHA_ADDR_DATA_OUT1 CHACHA_ADDR_BASE + 0x81 -#define CHACHA_ADDR_DATA_OUT2 CHACHA_ADDR_BASE + 0x82 -#define CHACHA_ADDR_DATA_OUT3 CHACHA_ADDR_BASE + 0x83 -#define CHACHA_ADDR_DATA_OUT4 CHACHA_ADDR_BASE + 0x84 -#define CHACHA_ADDR_DATA_OUT5 CHACHA_ADDR_BASE + 0x85 -#define CHACHA_ADDR_DATA_OUT6 CHACHA_ADDR_BASE + 0x86 -#define CHACHA_ADDR_DATA_OUT7 CHACHA_ADDR_BASE + 0x87 -#define CHACHA_ADDR_DATA_OUT8 CHACHA_ADDR_BASE + 0x88 -#define CHACHA_ADDR_DATA_OUT9 CHACHA_ADDR_BASE + 0x89 -#define CHACHA_ADDR_DATA_OUT10 CHACHA_ADDR_BASE + 0x8a -#define CHACHA_ADDR_DATA_OUT11 CHACHA_ADDR_BASE + 0x8b -#define CHACHA_ADDR_DATA_OUT12 CHACHA_ADDR_BASE + 0x8c -#define CHACHA_ADDR_DATA_OUT13 CHACHA_ADDR_BASE + 0x8d -#define CHACHA_ADDR_DATA_OUT14 CHACHA_ADDR_BASE + 0x8e -#define CHACHA_ADDR_DATA_OUT15 CHACHA_ADDR_BASE + 0x8f +#define CHACHA_ADDR_ROUNDS 0x0b + +#define CHACHA_ADDR_KEY0 0x10 +#define CHACHA_ADDR_KEY1 0x11 +#define CHACHA_ADDR_KEY2 0x12 +#define CHACHA_ADDR_KEY3 0x13 +#define CHACHA_ADDR_KEY4 0x14 +#define CHACHA_ADDR_KEY5 0x15 +#define CHACHA_ADDR_KEY6 0x16 +#define CHACHA_ADDR_KEY7 0x17 + +#define CHACHA_ADDR_IV0 0x20 +#define CHACHA_ADDR_IV1 0x21 + +#define CHACHA_ADDR_DATA_IN0 0x40 +#define CHACHA_ADDR_DATA_IN1 0x41 +#define CHACHA_ADDR_DATA_IN2 0x42 +#define CHACHA_ADDR_DATA_IN3 0x43 +#define CHACHA_ADDR_DATA_IN4 0x44 +#define CHACHA_ADDR_DATA_IN5 0x45 +#define CHACHA_ADDR_DATA_IN6 0x46 +#define CHACHA_ADDR_DATA_IN7 0x47 +#define CHACHA_ADDR_DATA_IN8 0x48 +#define CHACHA_ADDR_DATA_IN9 0x49 +#define CHACHA_ADDR_DATA_IN10 0x4a +#define CHACHA_ADDR_DATA_IN11 0x4b +#define CHACHA_ADDR_DATA_IN12 0x4c +#define CHACHA_ADDR_DATA_IN13 0x4d +#define CHACHA_ADDR_DATA_IN14 0x4e +#define CHACHA_ADDR_DATA_IN15 0x4f + +#define CHACHA_ADDR_DATA_OUT0 0x80 +#define CHACHA_ADDR_DATA_OUT1 0x81 +#define CHACHA_ADDR_DATA_OUT2 0x82 +#define CHACHA_ADDR_DATA_OUT3 0x83 +#define CHACHA_ADDR_DATA_OUT4 0x84 +#define CHACHA_ADDR_DATA_OUT5 0x85 +#define CHACHA_ADDR_DATA_OUT6 0x86 +#define CHACHA_ADDR_DATA_OUT7 0x87 +#define CHACHA_ADDR_DATA_OUT8 0x88 +#define CHACHA_ADDR_DATA_OUT9 0x89 +#define CHACHA_ADDR_DATA_OUT10 0x8a +#define CHACHA_ADDR_DATA_OUT11 0x8b +#define CHACHA_ADDR_DATA_OUT12 0x8c +#define CHACHA_ADDR_DATA_OUT13 0x8d +#define CHACHA_ADDR_DATA_OUT14 0x8e +#define CHACHA_ADDR_DATA_OUT15 0x8f // current name and version values #define CHACHA_NAME0 "chac" @@ -386,36 +366,35 @@ in order to map it into a 16-bit address space. // ----------------------------------------------------------------- -// MATH segment. +// Math cores // ----------------------------------------------------------------- -// Modexp core. -#define MODEXP_ADDR_BASE SEGMENT_OFFSET_MATH + (0x00 * CORE_SIZE) -#define MODEXP_ADDR_NAME0 MODEXP_ADDR_BASE + ADDR_NAME0 -#define MODEXP_ADDR_NAME1 MODEXP_ADDR_BASE + ADDR_NAME1 -#define MODEXP_ADDR_VERSION MODEXP_ADDR_BASE + ADDR_VERSION -#define MODEXP_ADDR_CTRL MODEXP_ADDR_BASE + ADDR_CTRL +// Modular exponentiation core +#define MODEXP_ADDR_NAME0 ADDR_NAME0 +#define MODEXP_ADDR_NAME1 ADDR_NAME1 +#define MODEXP_ADDR_VERSION ADDR_VERSION +#define MODEXP_ADDR_CTRL ADDR_CTRL #define MODEXP_CTRL_INIT_BIT 1 #define MODEXP_CTRL_NEXT_BIT 2 -#define MODEXP_ADDR_STATUS MODEXP_ADDR_BASE + ADDR_STATUS +#define MODEXP_ADDR_STATUS ADDR_STATUS -#define MODEXP_ADDR_DELAY MODEXP_ADDR_BASE + 0x13 +#define MODEXP_ADDR_DELAY 0x13 #define MODEXP_STATUS_READY 1 -#define MODEXP_MODULUS_LENGTH MODEXP_ADDR_BASE + 0x20 -#define MODEXP_EXPONENT_LENGTH MODEXP_ADDR_BASE + 0x21 -#define MODEXP_LENGTH MODEXP_ADDR_BASE + 0x22 +#define MODEXP_MODULUS_LENGTH 0x20 +#define MODEXP_EXPONENT_LENGTH 0x21 +#define MODEXP_LENGTH 0x22 -#define MODEXP_MODULUS_PTR_RST MODEXP_ADDR_BASE + 0x30 -#define MODEXP_MODULUS_DATA MODEXP_ADDR_BASE + 0x31 +#define MODEXP_MODULUS_PTR_RST 0x30 +#define MODEXP_MODULUS_DATA 0x31 -#define MODEXP_EXPONENT_PTR_RST MODEXP_ADDR_BASE + 0x40 -#define MODEXP_EXPONENT_DATA MODEXP_ADDR_BASE + 0x41 +#define MODEXP_EXPONENT_PTR_RST 0x40 +#define MODEXP_EXPONENT_DATA 0x41 -#define MODEXP_MESSAGE_PTR_RST MODEXP_ADDR_BASE + 0x50 -#define MODEXP_MESSAGE_DATA MODEXP_ADDR_BASE + 0x51 +#define MODEXP_MESSAGE_PTR_RST 0x50 +#define MODEXP_MESSAGE_DATA 0x51 -#define MODEXP_RESULT_PTR_RST MODEXP_ADDR_BASE + 0x60 -#define MODEXP_RESULT_DATA MODEXP_ADDR_BASE + 0x61 +#define MODEXP_RESULT_PTR_RST 0x60 +#define MODEXP_RESULT_DATA 0x61 #define MODEXP_NAME0 "mode" #define MODEXP_NAME1 "xp " @@ -423,30 +402,30 @@ in order to map it into a 16-bit address space. // Experimental ModexpS6 core. // XXX AT THE SAME CORE PREFIX - YOU CAN'T HAVE BOTH AT THE SAME TIME -#define MODEXPS6_ADDR_BASE SEGMENT_OFFSET_MATH + (0x00 * CORE_SIZE) -#define MODEXPS6_ADDR_NAME0 MODEXPS6_ADDR_BASE + ADDR_NAME0 -#define MODEXPS6_ADDR_NAME1 MODEXPS6_ADDR_BASE + ADDR_NAME1 -#define MODEXPS6_ADDR_VERSION MODEXPS6_ADDR_BASE + ADDR_VERSION -#define MODEXPS6_ADDR_CTRL MODEXPS6_ADDR_BASE + ADDR_CTRL +// Well, under the old scheme, anyway, remains to be seen with the new scheme +#define MODEXPS6_ADDR_NAME0 ADDR_NAME0 +#define MODEXPS6_ADDR_NAME1 ADDR_NAME1 +#define MODEXPS6_ADDR_VERSION ADDR_VERSION +#define MODEXPS6_ADDR_CTRL ADDR_CTRL #define MODEXPS6_CTRL_INIT_BIT 1 #define MODEXPS6_CTRL_NEXT_BIT 2 -#define MODEXPS6_ADDR_STATUS MODEXPS6_ADDR_BASE + ADDR_STATUS +#define MODEXPS6_ADDR_STATUS ADDR_STATUS /* 4096-bit operands are stored as 128 words of 32 bits */ #define MODEXPS6_OPERAND_SIZE 4096/32 -#define MODEXPS6_ADDR_REGISTERS MODEXPS6_ADDR_BASE + 0*MODEXPS6_OPERAND_SIZE -#define MODEXPS6_ADDR_OPERANDS MODEXPS6_ADDR_BASE + 4*MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_REGISTERS 0 * MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_OPERANDS 4 * MODEXPS6_OPERAND_SIZE #define MODEXPS6_ADDR_MODE MODEXPS6_ADDR_REGISTERS + 0x10 #define MODEXPS6_ADDR_MODULUS_WIDTH MODEXPS6_ADDR_REGISTERS + 0x11 #define MODEXPS6_ADDR_EXPONENT_WIDTH MODEXPS6_ADDR_REGISTERS + 0x12 /* addresses of block memories for operands */ -#define MODEXPS6_ADDR_MODULUS MODEXPS6_ADDR_OPERANDS + 0*MODEXPS6_OPERAND_SIZE -#define MODEXPS6_ADDR_MESSAGE MODEXPS6_ADDR_OPERANDS + 1*MODEXPS6_OPERAND_SIZE -#define MODEXPS6_ADDR_EXPONENT MODEXPS6_ADDR_OPERANDS + 2*MODEXPS6_OPERAND_SIZE -#define MODEXPS6_ADDR_RESULT MODEXPS6_ADDR_OPERANDS + 3*MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_MODULUS MODEXPS6_ADDR_OPERANDS + 0 * MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_MESSAGE MODEXPS6_ADDR_OPERANDS + 1 * MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_EXPONENT MODEXPS6_ADDR_OPERANDS + 2 * MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_RESULT MODEXPS6_ADDR_OPERANDS + 3 * MODEXPS6_OPERAND_SIZE #define MODEXPS6_NAME0 "mode" #define MODEXPS6_NAME1 "xps6" @@ -456,6 +435,16 @@ in order to map it into a 16-bit address space. //------------------------------------------------------------------ // Test case public functions //------------------------------------------------------------------ +struct core_info { + char name[8]; + char version[4]; + off_t base; + struct core_info *next; +}; +struct core_info *tc_core_first(char *name); +struct core_info *tc_core_next(struct core_info *node, char *name); +off_t tc_core_base(char *name); + void tc_set_debug(int onoff); int tc_write(off_t offset, const uint8_t *buf, size_t len); int tc_read(off_t offset, uint8_t *buf, size_t len); |