diff options
Diffstat (limited to 'i2c')
| -rw-r--r-- | i2c/build/Makefile | 102 | ||||
| -rw-r--r-- | i2c/rtl/novena_i2c.v | 18 |
2 files changed, 49 insertions, 71 deletions
diff --git a/i2c/build/Makefile b/i2c/build/Makefile index 1859da3..441b67a 100644 --- a/i2c/build/Makefile +++ b/i2c/build/Makefile @@ -1,70 +1,44 @@ -project = novena_i2c -vendor = xilinx -family = spartan6 -part = xc6slx45csg324-3 -top_module = novena_top -isedir = /opt/Xilinx/14.7/ISE_DS -xil_env = . $(isedir)/settings64.sh -ucf = ../ucf/novena_i2c.ucf +# Localize all the relative path awfulness in one variable. + +CORE_TREE := $(abspath ../../../..) + +# Figure out what the native word size is on the build host, because +# the XiLinx tools care for some reason. + +WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8') + +# Parameters to xilinx.mk. + +project = novena_eim +vendor = xilinx +family = spartan6 +part = xc6slx45csg324-3 +top_module = novena_top +isedir = /opt/Xilinx/14.7/ISE_DS +xil_env = . $(isedir)/settings$(WORD_SIZE).sh +ucf = ../ucf/$(project).ucf + +# Verilog files that always go with builds on this platform. vfiles = \ - ../rtl/novena_i2c.v \ - ../../common/rtl/novena_regs.v \ - ../../common/rtl/novena_clkmgr.v \ - ../../common/rtl/ipcore/clkmgr_dcm.v \ - ../../../common/core_selector/src/rtl/core_selector.v \ - ../../../common/core_selector/src/rtl/global_selector.v \ - ../../../common/core_selector/src/rtl/hash_selector.v \ - ../../../common/core_selector/src/rtl/rng_selector.v \ - ../../../common/core_selector/src/rtl/cipher_selector.v \ - ../../../common/core_selector/src/rtl/math_selector.v \ - ../../../../comm/i2c/src/rtl/i2c_regs.v \ - ../../../../comm/i2c/src/rtl/i2c_core.v \ - ../../../../comm/coretest/src/rtl/coretest.v \ - ../../../../hash/sha1/src/rtl/sha1.v \ - ../../../../hash/sha1/src/rtl/sha1_core.v \ - ../../../../hash/sha1/src/rtl/sha1_w_mem.v \ - ../../../../hash/sha256/src/rtl/sha256.v \ - ../../../../hash/sha256/src/rtl/sha256_core.v \ - ../../../../hash/sha256/src/rtl/sha256_k_constants.v \ - ../../../../hash/sha256/src/rtl/sha256_w_mem.v \ - ../../../../hash/sha512/src/rtl/sha512.v \ - ../../../../hash/sha512/src/rtl/sha512_core.v \ - ../../../../hash/sha512/src/rtl/sha512_h_constants.v \ - ../../../../hash/sha512/src/rtl/sha512_k_constants.v \ - ../../../../hash/sha512/src/rtl/sha512_w_mem.v \ - ../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \ - ../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \ - ../../../../rng/rosc_entropy/src/rtl/rosc.v \ - ../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \ - ../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \ - ../../../../rng/trng/src/rtl/trng.v \ - ../../../../rng/trng/src/rtl/trng_csprng.v \ - ../../../../rng/trng/src/rtl/trng_csprng_fifo.v \ - ../../../../rng/trng/src/rtl/trng_mixer.v \ - ../../../../cipher/aes/src/rtl/aes.v \ - ../../../../cipher/aes/src/rtl/aes_core.v \ - ../../../../cipher/aes/src/rtl/aes_decipher_block.v \ - ../../../../cipher/aes/src/rtl/aes_encipher_block.v \ - ../../../../cipher/aes/src/rtl/aes_inv_sbox.v \ - ../../../../cipher/aes/src/rtl/aes_key_mem.v \ - ../../../../cipher/aes/src/rtl/aes_sbox.v \ - ../../../../cipher/chacha/src/rtl/chacha.v \ - ../../../../cipher/chacha/src/rtl/chacha_core.v \ - ../../../../cipher/chacha/src/rtl/chacha_qr.v \ - ../../../../math/modexp/src/rtl/adder32.v \ - ../../../../math/modexp/src/rtl/blockmem1r1w.v \ - ../../../../math/modexp/src/rtl/blockmem2r1wptr.v \ - ../../../../math/modexp/src/rtl/blockmem2r1w.v \ - ../../../../math/modexp/src/rtl/blockmem2rptr1w.v \ - ../../../../math/modexp/src/rtl/modexp.v \ - ../../../../math/modexp/src/rtl/modexp_core.v \ - ../../../../math/modexp/src/rtl/montprod.v \ - ../../../../math/modexp/src/rtl/residue.v \ - ../../../../math/modexp/src/rtl/shl32.v \ - ../../../../math/modexp/src/rtl/shr32.v + $(CORE_TREE)/platform/novena/i2c/rtl/novena_i2c.v \ + $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \ + $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \ + $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \ + $(CORE_TREE)/platform/novena/config/core_selector.v \ + $(CORE_TREE)/comm/i2c/src/rtl/i2c_regs.v \ + $(CORE_TREE)/comm/i2c/src/rtl/i2c_core.v \ + $(CORE_TREE)/comm/coretest/src/rtl/coretest.v + +# Verilog files selected by the core configuration script. + +-include $(CORE_TREE)/platform/novena/config/core_vfiles.mk include xilinx.mk +# Fun extras for running verlator as a linter. + +VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME + lint: - verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v + verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v diff --git a/i2c/rtl/novena_i2c.v b/i2c/rtl/novena_i2c.v index f6230a0..db2c203 100644 --- a/i2c/rtl/novena_i2c.v +++ b/i2c/rtl/novena_i2c.v @@ -67,9 +67,14 @@ module novena_top // and implement the reset logic. // ---------------------------------------------------------------- wire sys_clk; - wire sys_rst; + wire sys_rst_n; - novena_clkmgr clkmgr + novena_clkmgr # + ( + .CLK_OUT_MUL (2), // 2..32 + .CLK_OUT_DIV (2) // 1..32 + ) + clkmgr ( .gclk_p(gclk_p_pin), .gclk_n(gclk_n_pin), @@ -77,7 +82,7 @@ module novena_top .reset_mcu_b(reset_mcu_b_pin), .sys_clk(sys_clk), - .sys_rst(sys_rst) + .sys_rst_n(sys_rst_n) ); @@ -96,7 +101,6 @@ module novena_top wire sda_int; wire clk = sys_clk; - wire reset_n = ~sys_rst; // Coretest connections. wire coretest_reset_n; @@ -127,7 +131,7 @@ module novena_top i2c_core i2c_core ( .clk(clk), - .reset(sys_rst), + .reset(~sys_rst_n), // active-high reset for this third-party module // External data interface .SCL(i2c_scl), @@ -149,7 +153,7 @@ module novena_top coretest coretest ( .clk(clk), - .reset_n(reset_n), + .reset_n(sys_rst_n), .rx_syn(i2c_rxd_syn), .rx_data(i2c_rxd_data), @@ -184,7 +188,7 @@ module novena_top core_selector cores ( .sys_clk(clk), - .sys_rst(sys_rst), + .sys_rst_n(sys_rst_n), .sys_eim_addr(sys_eim_addr), .sys_eim_wr(sys_eim_wr), |