diff options
Diffstat (limited to 'i2c/sw/trng_tester_i2c.c')
| -rw-r--r-- | i2c/sw/trng_tester_i2c.c | 421 |
1 files changed, 421 insertions, 0 deletions
diff --git a/i2c/sw/trng_tester_i2c.c b/i2c/sw/trng_tester_i2c.c new file mode 100644 index 0000000..a38f7fa --- /dev/null +++ b/i2c/sw/trng_tester_i2c.c @@ -0,0 +1,421 @@ +/* + * trng_tester.c + * -------------- + * This program sends several commands to the TRNG subsystem + * in order to verify the avalanche_entropy, rosc_entropy, and csprng cores. + * + * Note: This version of the program talks to the FPGA over an I2C bus. + * + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <string.h> +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <time.h> +#include <stdint.h> +#include <ctype.h> + +#include "tc_i2c.h" + +#define WAIT_STATS /* report number of status reads before core says "ready" */ + +int debug = 0; +int quiet = 0; +int num_words = 10; + +/* memory segments for core families */ +#define SEGMENT_OFFSET_GLOBALS 0x0000 +#define SEGMENT_OFFSET_HASHES 0x2000 +#define SEGMENT_OFFSET_RNGS 0x4000 +#define SEGMENT_OFFSET_CIPHERS 0x6000 + +/* addresses and codes common to all cores */ +#define ADDR_NAME0 0x00 +#define ADDR_NAME1 0x01 +#define ADDR_VERSION 0x02 + +/* At segment 0, we have board-level register and communication channel registers */ +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0000 +#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 +#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 +#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION +#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + 0xFF + +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0100 +#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 +#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 +#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION + +#define CORE_SIZE 0x100 + +/* addresses and codes for the TRNG cores */ +#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x00 * CORE_SIZE) +#define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 +#define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 +#define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION +#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + 0x10 +#define TRNG_CTRL_DISCARD 1 +#define TRNG_CTRL_TEST_MODE 2 +#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + 0x11 +/* no status bits defined */ +#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + 0x13 + +#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x05 * CORE_SIZE) +#define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 +#define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 +#define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION +#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + 0x10 +#define ENTROPY1_CTRL_ENABLE 1 +#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + 0x11 +#define ENTROPY1_STATUS_VALID 1 +#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + 0x20 +#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + 0x30 + +#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x06 * CORE_SIZE) +#define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 +#define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 +#define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION +#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + 0x10 +#define ENTROPY2_CTRL_ENABLE 1 +#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + 0x11 +#define ENTROPY2_STATUS_VALID 1 +#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + 0x18 +#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + 0x19 +#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + 0x20 +#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + 0x21 +#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + 0x22 + +#define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * CORE_SIZE) +#define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 +#define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 +#define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION +#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + 0x10 +#define MIXER_CTRL_ENABLE 1 +#define MIXER_CTRL_RESTART 2 +#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + 0x11 +/* no status bits defined */ +#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + 0x20 + +#define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * CORE_SIZE) +#define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 +#define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 +#define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION +#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + 0x10 +#define CSPRNG_CTRL_ENABLE 1 +#define CSPRNG_CTRL_SEED 2 +#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + 0x11 +#define CSPRNG_STATUS_VALID 1 +#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + 0x20 +#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + 0x40 +#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + 0x41 +#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + 0x42 + +/* ---------------- sanity test case ---------------- */ + +int TC0() +{ + uint8_t board_name0[4] = "PVT1"; + uint8_t board_name1[4] = " "; + uint8_t board_version[4] = "0.10"; + + uint8_t comm_name0[4] = "i2c "; + uint8_t comm_name1[4] = " "; + uint8_t comm_version[4] = "0.10"; + + uint8_t t[4]; + + if (!quiet) + printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); + + /* write current time into dummy register, then try to read it back + * to make sure that we can actually write something into EIM + */ + (void)time((time_t *)t); + if (tc_write(BOARD_ADDR_DUMMY, t, 4) != 0) + return 1; + + if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || + tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || + tc_expected(BOARD_ADDR_VERSION, board_version, 4) || + tc_expected(BOARD_ADDR_DUMMY, t, 4)) + return 1; + + if (!quiet) + printf("TC0-2: Reading name and version words from communications core.\n"); + + return + tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || + tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || + tc_expected(COMM_ADDR_VERSION, comm_version, 4); +} + +/* ---------------- trng test cases ---------------- */ + +/* TC1: Read name and version from trng core. */ +int TC1(void) +{ + uint8_t name0[4] = "trng"; + uint8_t name1[4] = " "; + uint8_t version[4] = "0.01"; + + if (!quiet) + printf("TC1: Reading name and version words from trng core.\n"); + + return + tc_expected(TRNG_ADDR_NAME0, name0, 4) || + tc_expected(TRNG_ADDR_NAME1, name1, 4) || + tc_expected(TRNG_ADDR_VERSION, version, 4); +} + +/* XXX test cases for setting blinkenlights? */ +/* XXX set 'discard' control bit, see if we read the same value */ + +/* ---------------- avalanche_entropy test cases ---------------- */ + +/* TC2: Read name and version from avalanche_entropy core. */ +int TC2(void) +{ + uint8_t name0[4] = "extn"; + uint8_t name1[4] = "oise"; + uint8_t version[4] = "0.10"; + + if (!quiet) + printf("TC2: Reading name and version words from avalanche_entropy core.\n"); + + return + tc_expected(ENTROPY1_ADDR_NAME0, name0, 4) || + tc_expected(ENTROPY1_ADDR_NAME1, name1, 4) || + tc_expected(ENTROPY1_ADDR_VERSION, version, 4); +} + +/* XXX clear 'enable' control bit, see if we read the same value */ + +/* TC3: Read random data from avalanche_entropy. */ +int TC3(void) +{ + int i, n; + unsigned long entropy; + + if (!quiet) + printf("TC3: Read random data from avalanche_entropy.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 10; + if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID, &n) != 0) + return 1; + /* read entropy data */ + if (tc_read(ENTROPY1_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) + return 1; + /* display entropy data */ + if (!debug) +#ifdef WAIT_STATS + printf("%08lx %d\n", entropy, n); +#else + printf("%08lx\n", entropy); +#endif + } + + return 0; +} + +/* ---------------- rosc_entropy test cases ---------------- */ + +/* TC4: Read name and version from rosc_entropy core. */ +int TC4(void) +{ + uint8_t name0[4] = "rosc"; + uint8_t name1[4] = " ent"; + uint8_t version[4] = "0.10"; + + if (!quiet) + printf("TC4: Reading name and version words from rosc_entropy core.\n"); + + return + tc_expected(ENTROPY2_ADDR_NAME0, name0, 4) || + tc_expected(ENTROPY2_ADDR_NAME1, name1, 4) || + tc_expected(ENTROPY2_ADDR_VERSION, version, 4); +} + +/* XXX clear 'enable' control bit, see if we read the same value */ + +/* TC5: Read random data from rosc_entropy. */ +int TC5(void) +{ + int i, n; + unsigned long entropy; + + if (!quiet) + printf("TC5: Read random data from rosc_entropy.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 10; + if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID, &n) != 0) + return 1; + /* read entropy data */ + if (tc_read(ENTROPY2_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) + return 1; + /* display entropy data */ + if (!debug) +#ifdef WAIT_STATS + printf("%08lx %d\n", entropy, n); +#else + printf("%08lx\n", entropy); +#endif + } + + return 0; +} + +/* ---------------- trng_csprng test cases ---------------- */ + +/* TC6: Read name and version from trng_csprng core. */ +int TC6(void) +{ + /* XXX csprng core currently doesn't have name/version registers */ + return 0; +} + +/* XXX clear 'enable' control bit, see if we read the same value */ +/* XXX set 'seed' control bit, see if we read the same value */ + +/* TC7: Read random data from trng_csprng. */ +int TC7(void) +{ + int i, n; + unsigned long random; + + if (!quiet) + printf("TC7: Read random data from trng_csprng.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 10; + if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID, &n) != 0) + return 1; + /* read random data */ + if (tc_read(CSPRNG_ADDR_RANDOM, (uint8_t *)&random, 4) != 0) + return 1; + /* display random data */ + if (!debug) +#ifdef WAIT_STATS + printf("%08lx %d\n", random, n); +#else + printf("%08lx\n", random); +#endif + } + + return 0; +} + +/* ---------------- main ---------------- */ + +int main(int argc, char *argv[]) +{ + typedef int (*tcfp)(void); + tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 }; + + char *usage = "Usage: %s [-h] [-d] [-q] [-n #] [-i I2C_device] [-a I2C_addr] tc...\n"; + char *dev = I2C_dev; + int addr = I2C_addr; + int i, j, opt; + + while ((opt = getopt(argc, argv, "h?dqn:i:a:")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + debug = 1; + break; + case 'q': + quiet = 1; + break; + case 'n': + num_words = atoi(optarg); + if (num_words <= 0) { + fprintf(stderr, "-n requires a positive integer argument\n"); + return EXIT_FAILURE; + } + break; + case 'i': + dev = optarg; + break; + case 'a': + addr = (int)strtol(optarg, NULL, 0); + if ((addr < 0x03) || (addr > 0x77)) { + fprintf(stderr, "addr must be between 0x03 and 0x77\n"); + return 1; + } + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + /* set up I2C */ + if (i2c_open(dev, addr) != 0) + return EXIT_FAILURE; + + /* no args == run all tests */ + if (optind >= argc) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + return EXIT_SUCCESS; + } + + /* run one or more tests (by number) or groups of tests (by name) */ + for (i = optind; i < argc; ++i) { + if (strcmp(argv[i], "all") == 0) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (isdigit(argv[i][0]) && + (((j = atoi(argv[i])) >= 0) && + (j < sizeof(all_tests)/sizeof(all_tests[0])))) { + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else { + fprintf(stderr, "unknown test case %s\n", argv[i]); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} |