diff options
Diffstat (limited to 'i2c/sw/cryptech_memory_map.h')
| -rw-r--r-- | i2c/sw/cryptech_memory_map.h | 119 |
1 files changed, 70 insertions, 49 deletions
diff --git a/i2c/sw/cryptech_memory_map.h b/i2c/sw/cryptech_memory_map.h index cf5cb89..5cf7f42 100644 --- a/i2c/sw/cryptech_memory_map.h +++ b/i2c/sw/cryptech_memory_map.h @@ -5,7 +5,7 @@ // The memory map for Cryptech cores. // // -// Author: Joachim Strombergson +// Authors: Joachim Strombergson, Paul Selkirk // Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -36,30 +36,48 @@ // //====================================================================== +// BASE_ADDR, SEGMENT_SIZE, and ADDR are defined in tc_[eim|i2c].h, +// which #includes this file. + +// default definitions from i2c, because defaults are good +#ifndef BASE_ADDR +#define BASE_ADDR 0 +#endif +#ifndef SEGMENT_SIZE +#define SEGMENT_SIZE 0x2000 +#endif +#ifndef ADDR +#define ADDR(x) (x) +#endif + +#ifndef bitsToBytes +#define bitsToBytes(x) (x / 8) +#endif + // Segments. -#define SEGMENT_OFFSET_GLOBALS 0x0000 -#define SEGMENT_OFFSET_HASHES 0x2000 -#define SEGMENT_OFFSET_RNGS 0x4000 -#define SEGMENT_OFFSET_CIPHERS 0x6000 +#define SEGMENT_OFFSET_GLOBALS BASE_ADDR + (0 * SEGMENT_SIZE) +#define SEGMENT_OFFSET_HASHES BASE_ADDR + (1 * SEGMENT_SIZE) +#define SEGMENT_OFFSET_RNGS BASE_ADDR + (2 * SEGMENT_SIZE) +#define SEGMENT_OFFSET_CIPHERS BASE_ADDR + (3 * SEGMENT_SIZE) // addresses and codes common to all cores -#define ADDR_NAME0 0x00 -#define ADDR_NAME1 0x01 -#define ADDR_VERSION 0x02 +#define ADDR_NAME0 ADDR(0x00) +#define ADDR_NAME1 ADDR(0x01) +#define ADDR_VERSION ADDR(0x02) //------------------------------------------------------------------ // Board segment. // Board-level registers and communication channel registers //------------------------------------------------------------------ -#define BOARD_CORE_SIZE 0x100 +#define BOARD_CORE_SIZE ADDR(0x100) #define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0 * BOARD_CORE_SIZE) #define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 #define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 #define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION -#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + 0xFF +#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + ADDR(0xFF) #define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (1 * BOARD_CORE_SIZE) #define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 @@ -70,17 +88,17 @@ //------------------------------------------------------------------ // Hashes segment. //------------------------------------------------------------------ -#define HASH_CORE_SIZE 0x100 +#define HASH_CORE_SIZE ADDR(0x100) // addresses and codes common to all hash cores */ -#define ADDR_CTRL 0x8 +#define ADDR_CTRL ADDR(0x8) #define CTRL_INIT_CMD 1 #define CTRL_NEXT_CMD 2 -#define ADDR_STATUS 9 +#define ADDR_STATUS ADDR(0x9) #define STATUS_READY_BIT 1 #define STATUS_VALID_BIT 2 -#define ADDR_BLOCK 0x10 -#define ADDR_DIGEST 0x20 // except SHA512 +#define ADDR_BLOCK ADDR(0x10) +#define ADDR_DIGEST ADDR(0x20) // except SHA512 // addresses and codes for the specific hash cores. #define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0 * HASH_CORE_SIZE) @@ -91,8 +109,9 @@ #define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS #define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK #define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST -#define SHA1_BLOCK_LEN 512 / 8 -#define SHA1_DIGEST_LEN 160 / 8 +#define SHA1_BLOCK_LEN bitsToBytes(512) +#define SHA1_LENGTH_LEN bitsToBytes(64) +#define SHA1_DIGEST_LEN bitsToBytes(160) #define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1 * HASH_CORE_SIZE) #define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 @@ -102,8 +121,9 @@ #define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS #define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK #define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST -#define SHA256_BLOCK_LEN 512 / 8 -#define SHA256_DIGEST_LEN 256 / 8 +#define SHA256_BLOCK_LEN bitsToBytes(512) +#define SHA256_LENGTH_LEN bitsToBytes(64) +#define SHA256_DIGEST_LEN bitsToBytes(256) #define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2 * HASH_CORE_SIZE) #define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 @@ -112,12 +132,13 @@ #define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL #define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS #define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK -#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + 0x40 -#define SHA512_BLOCK_LEN 1024 / 8 -#define SHA512_224_DIGEST_LEN 224 / 8 -#define SHA512_256_DIGEST_LEN 256 / 8 -#define SHA384_DIGEST_LEN 384 / 8 -#define SHA512_DIGEST_LEN 512 / 8 +#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + ADDR(0x40) +#define SHA512_BLOCK_LEN bitsToBytes(1024) +#define SHA512_LENGTH_LEN bitsToBytes(128) +#define SHA512_224_DIGEST_LEN bitsToBytes(224) +#define SHA512_256_DIGEST_LEN bitsToBytes(256) +#define SHA384_DIGEST_LEN bitsToBytes(384) +#define SHA512_DIGEST_LEN bitsToBytes(512) #define MODE_SHA_512_224 0 << 2 #define MODE_SHA_512_256 1 << 2 #define MODE_SHA_384 2 << 2 @@ -127,69 +148,69 @@ // ----------------------------------------------------------------- // TRNG segment. // ----------------------------------------------------------------- -#define TRNG_CORE_SIZE 0x100 +#define TRNG_CORE_SIZE ADDR(0x100) // addresses and codes for the TRNG cores */ #define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0 * TRNG_CORE_SIZE) #define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 #define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 #define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION -#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + 0x10 +#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + ADDR(0x10) #define TRNG_CTRL_DISCARD 1 #define TRNG_CTRL_TEST_MODE 2 -#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + 0x11 +#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + ADDR(0x11) // no status bits defined (yet) -#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + 0x13 +#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + ADDR(0x13) #define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (5 * TRNG_CORE_SIZE) #define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 #define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 #define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION -#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + 0x10 +#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + ADDR(0x10) #define ENTROPY1_CTRL_ENABLE 1 -#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + 0x11 +#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + ADDR(0x11) #define ENTROPY1_STATUS_VALID 1 -#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + 0x20 -#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + 0x30 +#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + ADDR(0x20) +#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + ADDR(0x30) #define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (6 * TRNG_CORE_SIZE) #define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 #define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 #define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION -#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + 0x10 +#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + ADDR(0x10) #define ENTROPY2_CTRL_ENABLE 1 -#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + 0x11 +#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + ADDR(0x11) #define ENTROPY2_STATUS_VALID 1 -#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + 0x18 -#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + 0x19 -#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + 0x20 -#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + 0x21 -#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + 0x22 +#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + ADDR(0x18) +#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + ADDR(0x19) +#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + ADDR(0x20) +#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + ADDR(0x21) +#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + ADDR(0x22) #define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * TRNG_CORE_SIZE) #define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 #define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 #define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION -#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + 0x10 +#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + ADDR(0x10) #define MIXER_CTRL_ENABLE 1 #define MIXER_CTRL_RESTART 2 -#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + 0x11 +#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + ADDR(0x11) // no status bits defined (yet) -#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + 0x20 +#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + ADDR(0x20) #define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * TRNG_CORE_SIZE) #define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 #define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 #define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION -#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + 0x10 +#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + ADDR(0x10) #define CSPRNG_CTRL_ENABLE 1 #define CSPRNG_CTRL_SEED 2 -#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + 0x11 +#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + ADDR(0x11) #define CSPRNG_STATUS_VALID 1 -#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + 0x20 -#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + 0x40 -#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + 0x41 -#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + 0x42 +#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + ADDR(0x20) +#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + ADDR(0x40) +#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + ADDR(0x41) +#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + ADDR(0x42) //====================================================================== // EOF cryptech_memory_map.h |