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-rw-r--r--fmc/build/Makefile47
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diff --git a/fmc/build/Makefile b/fmc/build/Makefile
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+# Localize all the relative path awfulness in one variable.
+
+CORE_TREE := $(abspath ../../../..)
+
+# Figure out what the native word size is on the build host, because
+# the XiLinx tools care for some reason.
+
+WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+
+# Parameters to xilinx.mk.
+
+project = novena_fmc
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings$(WORD_SIZE).sh
+ucf = ../ucf/$(project).ucf
+
+# Verilog files that always go with builds on this platform.
+
+vfiles = \
+ $(CORE_TREE)/platform/novena/fmc/rtl/novena_fmc_top.v \
+ $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
+ $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
+ $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
+ $(CORE_TREE)/platform/novena/config/core_selector.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_regs.v
+
+# Verilog files selected by the core configuration script.
+
+-include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
+
+include xilinx.mk
+
+# Fun extras for running verlator as a linter.
+
+VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
+
+lint:
+ verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v