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-rw-r--r--eim/build/Makefile4
-rw-r--r--eim/rtl/novena_eim.v23
2 files changed, 16 insertions, 11 deletions
diff --git a/eim/build/Makefile b/eim/build/Makefile
index 630faa9..a7eec60 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -7,7 +7,7 @@ CORE_TREE := $(abspath ../../../..)
WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
-# Parameters to xilinkx.mk.
+# Parameters to xilinx.mk.
project = novena_eim
vendor = xilinx
@@ -24,7 +24,7 @@ vfiles = \
$(CORE_TREE)/platform/novena/eim/rtl/novena_eim.v \
$(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
$(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
- $(CORE_TREE)/platform/novena/common/rtl/ipcore/clkmgr_dcm.v \
+ $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
$(CORE_TREE)/platform/novena/config/core_selector.v \
$(CORE_TREE)/comm/eim/src/rtl/cdc_bus_pulse.v \
$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter_cdc.v \
diff --git a/eim/rtl/novena_eim.v b/eim/rtl/novena_eim.v
index c774b6c..8feec20 100644
--- a/eim/rtl/novena_eim.v
+++ b/eim/rtl/novena_eim.v
@@ -75,18 +75,23 @@ module novena_top
// and implement the reset logic.
// ----------------------------------------------------------------
wire sys_clk;
- wire sys_rst;
+ wire sys_rst_n;
wire eim_bclk_buf;
- novena_clkmgr clkmgr
+ novena_clkmgr #
(
- .gclk_p(gclk_p_pin),
- .gclk_n(gclk_n_pin),
+ .CLK_OUT_MUL (2), // 2..32
+ .CLK_OUT_DIV (2) // 1..32
+ )
+ clkmgr
+ (
+ .gclk_p (gclk_p_pin),
+ .gclk_n (gclk_n_pin),
- .reset_mcu_b(reset_mcu_b_pin),
+ .reset_mcu_b (reset_mcu_b_pin),
- .sys_clk(sys_clk),
- .sys_rst(sys_rst)
+ .sys_clk (sys_clk),
+ .sys_rst_n (sys_rst_n)
);
@@ -123,7 +128,7 @@ module novena_top
.eim_wait_n(eim_wait_n),
.sys_clk(sys_clk),
- .sys_rst(sys_rst),
+ .sys_rst_n(sys_rst_n),
.sys_eim_addr(sys_eim_addr),
.sys_eim_wr(sys_eim_wr),
@@ -148,7 +153,7 @@ module novena_top
core_selector cores
(
.sys_clk(sys_clk),
- .sys_rst(sys_rst),
+ .sys_rst_n(sys_rst_n),
.sys_eim_addr(sys_eim_addr),
.sys_eim_wr(sys_eim_wr),