aboutsummaryrefslogtreecommitdiff
path: root/eim
diff options
context:
space:
mode:
Diffstat (limited to 'eim')
-rw-r--r--eim/build/xilinx.mk16
-rw-r--r--eim/rtl/novena_eim.v4
2 files changed, 10 insertions, 10 deletions
diff --git a/eim/build/xilinx.mk b/eim/build/xilinx.mk
index 8a81ef9..7a8d9d4 100644
--- a/eim/build/xilinx.mk
+++ b/eim/build/xilinx.mk
@@ -1,6 +1,6 @@
# The top level module should define the variables below then include
# this file. The files listed should be in the same directory as the
-# Makefile.
+# Makefile.
#
# variable description
# ---------- -------------
@@ -11,7 +11,7 @@
# vfiles all local .v files
# xilinx_cores all local .xco files
# vendor vendor of FPGA (xilinx, altera, etc.)
-# family FPGA device family (spartan3e)
+# family FPGA device family (spartan3e)
# part FPGA part name (xc4vfx12-10-sf363)
# flashsize size of flash for mcs file (16384)
# optfile (optional) xst extra opttions file to put in .scr
@@ -40,7 +40,7 @@ xil_env ?= . $(isedir)/settings32.sh
flashsize ?= 8192
ucf ?= $(project).ucf
-libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
+libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
mkfiles = $(libmks) xilinx.mk
include $(libmks)
@@ -110,9 +110,9 @@ $(project)_par.ncd: $(project).ncd
:; \
else \
$(MAKE) etwr; \
- fi
-junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
-junk += $(project)_par_pad.csv $(project)_par_pad.txt
+ fi
+junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
+junk += $(project)_par_pad.csv $(project)_par_pad.txt
junk += $(project)_par.grf $(project)_par.ptwx
junk += $(project)_par.unroutes $(project)_par.xpi
@@ -126,7 +126,7 @@ $(project).ncd: $(project).ngd
$(xil_env); \
map $(intstyle) $(map_opts) $$smartguide $<
junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
-junk += smartguide.ncd $(project).psr
+junk += smartguide.ncd $(project).psr
junk += $(project)_summary.xml $(project)_usage.xml
$(project).ngd: $(project).ngc $(ucf)
@@ -135,7 +135,7 @@ junk += $(project).ngd $(project).bld
$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj
$(xil_env); xst $(intstyle) -ifn $(project).scr
-junk += xlnx_auto* $(top_module).lso $(project).srp
+junk += xlnx_auto* $(top_module).lso $(project).srp
junk += netlist.lst xst $(project).ngc
$(project).prj: $(vfiles) $(mkfiles)
diff --git a/eim/rtl/novena_eim.v b/eim/rtl/novena_eim.v
index 1a1b1f6..c774b6c 100644
--- a/eim/rtl/novena_eim.v
+++ b/eim/rtl/novena_eim.v
@@ -56,7 +56,7 @@ module novena_top
input wire eim_bclk, // EIM burst clock. Started by the CPU.
input wire eim_cs0_n, // Chip select (active low).
inout wire [15 : 0] eim_da, // Bidirectional address and data port.
- input wire [18: 16] eim_a, // MSB part of address port.
+ input wire [18: 16] eim_a, // MSB part of address port.
input wire eim_lba_n, // Latch address signal (active low).
input wire eim_wr_n, // write enable signal (active low).
input wire eim_oe_n, // output enable signal (active low).
@@ -158,7 +158,7 @@ module novena_top
.noise(ct_noise),
.debug(ct_led)
- );
+ );
//----------------------------------------------------------------