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-rw-r--r--eim/rtl/novena_eim.v182
-rw-r--r--eim/rtl/novena_regs.v129
2 files changed, 311 insertions, 0 deletions
diff --git a/eim/rtl/novena_eim.v b/eim/rtl/novena_eim.v
new file mode 100644
index 0000000..fbff86c
--- /dev/null
+++ b/eim/rtl/novena_eim.v
@@ -0,0 +1,182 @@
+//======================================================================
+//
+// novena_top.v
+// ------------
+// Top module for the Cryptech Novena FPGA framework. This design
+// allow us to run the EIM interface at one clock and cores including
+// core selector with the always present global clock.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module novena_top
+ (
+ // Differential input for 50 MHz general clock.
+ input wire gclk_p_pin,
+ input wire gclk_n_pin,
+
+ // Reset controlled by the CPU.
+ // this must be configured as input w/pullup
+ input wire reset_mcu_b_pin,
+
+ // Cryptech avalanche noise board input and LED outputs
+ input wire ct_noise,
+ output wire [7 : 0] ct_led,
+
+ // EIM interface
+ input wire eim_bclk, // EIM burst clock. Started by the CPU.
+ input wire eim_cs0_n, // Chip select (active low).
+ inout wire [15 : 0] eim_da, // Bidirectional address and data port.
+ input wire [18: 16] eim_a, // MSB part of address port.
+ input wire eim_lba_n, // Latch address signal (active low).
+ input wire eim_wr_n, // write enable signal (active low).
+ input wire eim_oe_n, // output enable signal (active low).
+ output wire eim_wait_n, // Data wait signal (active low).
+
+ // Novena utility ports
+ output wire apoptosis_pin, // Hold low to not restart after config.
+ output wire led_pin // LED on edge close to the FPGA.
+ );
+
+
+ //----------------------------------------------------------------
+ // Clock Manager
+ //
+ // Clock manager is used to generate SYS_CLK from GCLK
+ // and implement the reset logic.
+ // ----------------------------------------------------------------
+ wire sys_clk;
+ wire sys_rst;
+ wire eim_bclk_buf;
+
+ novena_clkmgr clkmgr
+ (
+ .gclk_p(gclk_p_pin),
+ .gclk_n(gclk_n_pin),
+
+ .reset_mcu_b(reset_mcu_b_pin),
+
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst)
+ );
+
+
+ //
+ // BCLK BUFG
+ //
+ BUFG BUFG_BCLK
+ (
+ .I(eim_bclk),
+ .O(eim_bclk_buf)
+ );
+
+
+ //----------------------------------------------------------------
+ // EIM Interface
+ //
+ // EIM subsystem handles all data transfer to/from CPU via EIM bus.
+ //----------------------------------------------------------------
+ wire [16: 0] sys_eim_addr;
+ wire sys_eim_wr;
+ wire sys_eim_rd;
+ wire [31: 0] sys_eim_dout;
+ wire [31: 0] sys_eim_din;
+
+ eim eim
+ (
+ .eim_bclk(eim_bclk_buf),
+ .eim_cs0_n(eim_cs0_n),
+ .eim_da(eim_da),
+ .eim_a(eim_a),
+ .eim_lba_n(eim_lba_n),
+ .eim_wr_n(eim_wr_n),
+ .eim_oe_n(eim_oe_n),
+ .eim_wait_n(eim_wait_n),
+
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .sys_eim_addr(sys_eim_addr),
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
+ .sys_eim_dout(sys_eim_dout),
+ .sys_eim_din(sys_eim_din),
+
+ .led_pin(led_pin)
+ );
+
+
+ //----------------------------------------------------------------
+ // Core Selector
+ //
+ // This multiplexer is used to map different types of cores, such as
+ // hashes, RNGs and ciphers to different regions (segments) of memory.
+ //----------------------------------------------------------------
+ core_selector cores
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .sys_eim_addr(sys_eim_addr),
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
+
+ .sys_write_data(sys_eim_dout),
+ .sys_read_data(sys_eim_din)
+ );
+
+
+ //----------------------------------------------------------------
+ // Cryptech Logic
+ //
+ // Logic specific to the Cryptech use of the Novena.
+ // Currently we just hard wire the LED outputs.
+ //----------------------------------------------------------------
+ assign ct_led = {8{ct_noise}};
+
+
+ //----------------------------------------------------------------
+ // Novena Patch
+ //
+ // Patch logic to keep the Novena board happy.
+ // The apoptosis_pin pin must be kept low or the whole board
+ // (more exactly the CPU) will be reset after the FPGA has
+ // been configured.
+ //----------------------------------------------------------------
+ assign apoptosis_pin = 1'b0;
+
+
+endmodule
+
+//======================================================================
+// EOF novena_top.v
+//======================================================================
diff --git a/eim/rtl/novena_regs.v b/eim/rtl/novena_regs.v
new file mode 100644
index 0000000..f14e113
--- /dev/null
+++ b/eim/rtl/novena_regs.v
@@ -0,0 +1,129 @@
+//======================================================================
+//
+// novena_regs.v
+// -------------
+// Global registers for the Cryptech Novena FPGA framework.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+`timescale 1ns / 1ps
+
+module board_regs
+ (
+ input wire clk,
+ input wire rst,
+
+ input wire cs,
+ input wire we,
+
+ input wire [ 7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ // API addresses.
+ localparam ADDR_CORE_NAME0 = 8'h00;
+ localparam ADDR_CORE_NAME1 = 8'h01;
+ localparam ADDR_CORE_VERSION = 8'h02;
+ localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
+
+ // Core ID constants.
+ localparam CORE_NAME0 = 32'h50565431; // "PVT1"
+ localparam CORE_NAME1 = 32'h20202020; // " "
+ localparam CORE_VERSION = 32'h302e3130; // "0.10"
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31: 0] tmp_read_data;
+
+ // dummy register to check that you can actually write something
+ reg [31: 0] reg_dummy;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+
+
+ //----------------------------------------------------------------
+ // Access Handler
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ //
+ if (rst)
+ reg_dummy <= {32{1'b0}};
+ else if (cs) begin
+ //
+ if (we) begin
+ //
+ // WRITE handler
+ //
+ case (address)
+ ADDR_DUMMY_REG:
+ reg_dummy <= write_data;
+ endcase
+ //
+ end else begin
+ //
+ // READ handler
+ //
+ case (address)
+ ADDR_CORE_NAME0:
+ tmp_read_data <= CORE_NAME0;
+ ADDR_CORE_NAME1:
+ tmp_read_data <= CORE_NAME1;
+ ADDR_CORE_VERSION:
+ tmp_read_data <= CORE_VERSION;
+ ADDR_DUMMY_REG:
+ tmp_read_data <= reg_dummy;
+ //
+ default:
+ tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ endcase
+ //
+ end
+ //
+ end
+
+endmodule
+
+//======================================================================
+// EOF novena_regs.v
+//======================================================================