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-rw-r--r--eim/build/Makefile25
1 files changed, 20 insertions, 5 deletions
diff --git a/eim/build/Makefile b/eim/build/Makefile
index baefa7f..00d8604 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -1,6 +1,13 @@
-core_tree := $(abspath ../../../..)
+# Localize all the relative path awfulness in one variable.
-word_size := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+CORE_TREE := $(abspath ../../../..)
+
+# Figure out what the native word size is on the build host, because
+# the XiLinx tools care for some reason.
+
+WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+
+# Parameters to xilinkx.mk.
project = novena_eim
vendor = xilinx
@@ -8,8 +15,10 @@ family = spartan6
part = xc6slx45csg324-3
top_module = novena_top
isedir = /opt/Xilinx/14.7/ISE_DS
-xil_env = . $(isedir)/settings$(word_size).sh
-ucf = ../ucf/novena_eim.ucf
+xil_env = . $(isedir)/settings$(WORD_SIZE).sh
+ucf = ../ucf/$(project).ucf
+
+# Verilog files that always go with builds on this platform.
vfiles = \
$(core_tree)/platform/novena/eim/rtl/novena_eim.v \
@@ -25,9 +34,15 @@ vfiles = \
$(core_tree)/comm/eim/src/rtl/eim_regs.v \
$(core_tree)/comm/eim/src/rtl/eim.v
+# Verilog files selected by the core configuration script.
+
include $(core_tree)/platform/novena/config/core_vfiles.mk
include xilinx.mk
+# Fun extras for running verlator as a linter.
+
+VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
+
lint:
- verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v
+ verilator ${VERILATOR_FLAGS} $(vfiles) $(core_tree)/platform/novena/common/rtl/lint-dummy.v