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-rw-r--r--config/config.cfg17
-rwxr-xr-xconfig/config.py99
-rw-r--r--config/core_selector.v43
3 files changed, 85 insertions, 74 deletions
diff --git a/config/config.cfg b/config/config.cfg
index a4120b1..7e4571c 100644
--- a/config/config.cfg
+++ b/config/config.cfg
@@ -1,6 +1,6 @@
# Config file for the Cryptech Novena FPGA framework.
#
-# At present, there are four kinds of variables in this file:
+# Variables used in this file:
#
# default-section: Name of the configuration to build if the user
# doesn't specify one. Only meaningful in the default section.
@@ -16,6 +16,16 @@
# this core. This has no effect on the generated core_selector.v
# file, and has no effect at all if an instance of a core named here
# is already included in the build.
+#
+# reset_high: boolean indicating whether the core uses active reset.
+#
+# error_wire: boolean indicating whether the core wants a error wire.
+#
+# block_memory: boolean indicating whether the core uses block memory.
+# Effect of this is a bit strange: setting it triggers generation of
+# a one-cycle timing delay for every core in this build that does
+# *not* use block memory. When no cores in the build use block
+# memory, the delay isn't necessary and is therefore omitted.
[default]
default-section = rsa
@@ -86,7 +96,9 @@ vfiles =
cipher/chacha/src/rtl/chacha_qr.v
[modexps6]
-reset_high = true
+block_memory = yes
+reset_high = yes
+error_wire = no
vfiles =
math/modexps6/src/rtl/modexps6_adder64_carry32.v
math/modexps6/src/rtl/modexps6_buffer_core.v
@@ -101,6 +113,7 @@ vfiles =
math/modexps6/src/rtl/ipcore/subtractor_s6.v
[modexp]
+error_wire = no
vfiles =
math/modexp/src/rtl/adder.v
math/modexp/src/rtl/blockmem1r1w.v
diff --git a/config/config.py b/config/config.py
index 3cb69db..1c5e5d0 100755
--- a/config/config.py
+++ b/config/config.py
@@ -36,35 +36,24 @@ Generate core_selector.v and core_vfiles.mk for a set of cores.
# two-level (no segment) scheme and handle modexps6 as a set of four
# contiguous "cores" with a 10-bit composite register selector.
-# Gah: the TRNG core's internal multiplexer doesn't allocate cores
+# At present, TRNG core's internal multiplexer doesn't allocate cores
# contiguously, there's a gap, and one just has to know what the
-# offsets are. So we need to adjust for all of that. Feh. In theory
-# we could hide the gap from the outside world, as it's just a matter
-# of (magic) constant offsets on top of the ones we're already
-# fiddling with in the core_selector mux. See
-# core/rng/trng/src/rtl/trng.v for the authoritative list, but the
-# magic offsets for the high 4 bits of the 12-bit TRNG address are:
+# offsets are. Current theory is that we'll fix the TRNG core to get
+# rid of this problem, but for now the workaround requires this script
+# to know the magic offsets for the high 4 bits of the 12-bit TRNG
+# address:
#
-# 0: trng
-# 1: -
-# 2: -
-# 3: -
-# 4: -
-# 5: entropy1 (avalanche)
-# 6: entropy2 (rosc)
-# 7: -
-# 8: -
-# 9: -
-# a: mixer
-# b: csprng
-# c: -
-# d: -
-# e: -
-# f: -
-
-# The modexps6 core also drags in a one clock cycle delay to other
-# cores, to compensate for the extra clock cycle consumed by the block
-# memories used in the modexps6 core.
+# 0x0: trng
+# 0x5: entropy1 (avalanche)
+# 0x6: entropy2 (rosc)
+# 0xa: mixer
+# 0xb: csprng
+
+# The modexps6 core drags in a one clock cycle delay to other cores,
+# to compensate for the extra clock cycle consumed by the block
+# memories used in the modexps6 core. We probably want a general
+# solution for this, because we're going to run into this problem for
+# any core that handles arguments big enough to require block memory.
# To Do:
#
@@ -123,6 +112,8 @@ def main():
for core in cores:
core.configure(cfg)
+ Core.need_one_cycle_delay = any(core.block_memory for core in cores)
+
args.verilog.write(createModule_template.format(
addrs = "".join(core.createAddr() for core in cores),
insts = "".join(core.createInstance() for core in cores),
@@ -172,15 +163,22 @@ class Core(object):
_instance_count = {}
- # Map from core name to subclass for the special case cores.
+ # Class variable mapping core name to subclass for special cases.
special_class = {}
+ # Class variable recording whether we need a one-cycle delay to
+ # compensate for block memories.
+
+ need_one_cycle_delay = False
+
def __init__(self, name):
self.name = name
self.core_number = None
self.vfiles = []
self.reset_high = False
+ self.error_wire = True
+ self.block_memory = False
self.instance_number = self._instance_count.get(name, 0)
self._instance_count[name] = self.instance_number + 1
@@ -199,6 +197,8 @@ class Core(object):
if required not in self._instance_count:
self.vfiles.extend(cfg.getvalues(required, "vfiles"))
self.reset_high = cfg.getboolean(self.name, "reset_high", self.reset_high)
+ self.error_wire = cfg.getboolean(self.name, "error_wire", self.error_wire)
+ self.block_memory = cfg.getboolean(self.name, "block_memory", self.block_memory)
@property
def instance_name(self):
@@ -215,6 +215,22 @@ class Core(object):
def reset_pin(self):
return ".rst(sys_rst)" if self.reset_high else ".reset_n(~sys_rst)"
+ @property
+ def error_port(self):
+ return ",\n .error(error_{core.instance_name})".format(core = self) if self.error_wire else ""
+
+ @property
+ def one_cycle_delay(self):
+ return one_cycle_delay_template.format(core = self) if self.need_one_cycle_delay and not self.block_memory else ""
+
+ @property
+ def mux_data_reg(self):
+ return "read_data_" + self.instance_name + ("_reg" if self.need_one_cycle_delay and not self.block_memory else "")
+
+ @property
+ def mux_error_reg(self):
+ return "error_" + self.instance_name if self.error_wire else "0"
+
def createInstance(self):
return createInstance_template_generic.format(core = self)
@@ -300,7 +316,7 @@ class ModExpS6Core(Core):
return createInstance_template_ModExpS6.format(core = self)
def createMux(self):
- return createMux_modexps6_template.format(core = self)
+ return createMux_modexps6_template.format(core = self, core0 = self)
# Hook special classes in as handlers for the cores that require them.
@@ -341,14 +357,10 @@ createInstance_template_generic = """\
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_{core.instance_name}),
- .error(error_{core.instance_name})
+ .read_data(read_data_{core.instance_name}){core.error_port}
);
- reg [31: 0] read_data_{core.instance_name}_reg;
- always @(posedge sys_clk)
- read_data_{core.instance_name}_reg <= read_data_{core.instance_name};
-
+{core.one_cycle_delay}
"""
@@ -409,11 +421,16 @@ createInstance_template_TRNG = """\
.debug(debug)
);
+{core.one_cycle_delay}
+
+"""
+
+# Template for one-cycle delay code.
+
+one_cycle_delay_template = """\
reg [31: 0] read_data_{core.instance_name}_reg;
always @(posedge sys_clk)
read_data_{core.instance_name}_reg <= read_data_{core.instance_name};
-
-
"""
# Template for .createMux() methods.
@@ -421,8 +438,8 @@ createInstance_template_TRNG = """\
createMux_template = """\
CORE_ADDR_{core.upper_instance_name}:
begin
- sys_read_data_mux = read_data_{core0.instance_name}_reg;
- sys_error_mux = error_{core0.instance_name};
+ sys_read_data_mux = {core0.mux_data_reg};
+ sys_error_mux = {core0.mux_error_reg};
end
"""
@@ -434,8 +451,8 @@ createMux_modexps6_template = """\
CORE_ADDR_{core.upper_instance_name} + 2,
CORE_ADDR_{core.upper_instance_name} + 3:
begin
- sys_read_data_mux = read_data_{core.instance_name};
- sys_error_mux = 0;
+ sys_read_data_mux = {core0.mux_data_reg};
+ sys_error_mux = {core0.mux_error_reg};
end
"""
diff --git a/config/core_selector.v b/config/core_selector.v
index 90b688e..0f60771 100644
--- a/config/core_selector.v
+++ b/config/core_selector.v
@@ -62,9 +62,6 @@ module core_selector
.error(error_board_regs)
);
- reg [31: 0] read_data_board_regs_reg;
- always @(posedge sys_clk)
- read_data_board_regs_reg <= read_data_board_regs;
//----------------------------------------------------------------
@@ -88,9 +85,6 @@ module core_selector
.error(error_comm_regs)
);
- reg [31: 0] read_data_comm_regs_reg;
- always @(posedge sys_clk)
- read_data_comm_regs_reg <= read_data_comm_regs;
//----------------------------------------------------------------
@@ -114,9 +108,6 @@ module core_selector
.error(error_sha256)
);
- reg [31: 0] read_data_sha256_reg;
- always @(posedge sys_clk)
- read_data_sha256_reg <= read_data_sha256;
//----------------------------------------------------------------
@@ -140,9 +131,6 @@ module core_selector
.error(error_aes)
);
- reg [31: 0] read_data_aes_reg;
- always @(posedge sys_clk)
- read_data_aes_reg <= read_data_aes;
//----------------------------------------------------------------
@@ -170,9 +158,6 @@ module core_selector
.debug(debug)
);
- reg [31: 0] read_data_trng_reg;
- always @(posedge sys_clk)
- read_data_trng_reg <= read_data_trng;
//----------------------------------------------------------------
@@ -192,13 +177,9 @@ module core_selector
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_modexp),
- .error(error_modexp)
+ .read_data(read_data_modexp)
);
- reg [31: 0] read_data_modexp_reg;
- always @(posedge sys_clk)
- read_data_modexp_reg <= read_data_modexp;
@@ -215,53 +196,53 @@ module core_selector
case (addr_core_num)
CORE_ADDR_BOARD_REGS:
begin
- sys_read_data_mux = read_data_board_regs_reg;
+ sys_read_data_mux = read_data_board_regs;
sys_error_mux = error_board_regs;
end
CORE_ADDR_COMM_REGS:
begin
- sys_read_data_mux = read_data_comm_regs_reg;
+ sys_read_data_mux = read_data_comm_regs;
sys_error_mux = error_comm_regs;
end
CORE_ADDR_SHA256:
begin
- sys_read_data_mux = read_data_sha256_reg;
+ sys_read_data_mux = read_data_sha256;
sys_error_mux = error_sha256;
end
CORE_ADDR_AES:
begin
- sys_read_data_mux = read_data_aes_reg;
+ sys_read_data_mux = read_data_aes;
sys_error_mux = error_aes;
end
CORE_ADDR_TRNG:
begin
- sys_read_data_mux = read_data_trng_reg;
+ sys_read_data_mux = read_data_trng;
sys_error_mux = error_trng;
end
CORE_ADDR_AVALANCHE_ENTROPY:
begin
- sys_read_data_mux = read_data_trng_reg;
+ sys_read_data_mux = read_data_trng;
sys_error_mux = error_trng;
end
CORE_ADDR_ROSC_ENTROPY:
begin
- sys_read_data_mux = read_data_trng_reg;
+ sys_read_data_mux = read_data_trng;
sys_error_mux = error_trng;
end
CORE_ADDR_TRNG_MIXER:
begin
- sys_read_data_mux = read_data_trng_reg;
+ sys_read_data_mux = read_data_trng;
sys_error_mux = error_trng;
end
CORE_ADDR_TRNG_CSPRNG:
begin
- sys_read_data_mux = read_data_trng_reg;
+ sys_read_data_mux = read_data_trng;
sys_error_mux = error_trng;
end
CORE_ADDR_MODEXP:
begin
- sys_read_data_mux = read_data_modexp_reg;
- sys_error_mux = error_modexp;
+ sys_read_data_mux = read_data_modexp;
+ sys_error_mux = 0;
end
default:
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 01:49:09 +0000