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-rwxr-xr-xconfig/config.py11
-rw-r--r--config/core_selector.v38
2 files changed, 37 insertions, 12 deletions
diff --git a/config/config.py b/config/config.py
index 1c5e5d0..0f3818f 100755
--- a/config/config.py
+++ b/config/config.py
@@ -112,7 +112,14 @@ def main():
for core in cores:
core.configure(cfg)
- Core.need_one_cycle_delay = any(core.block_memory for core in cores)
+ if False:
+
+ # For some reason, attempting to optimize out the delay
+ # code entirely results in a non-working bitstream. Don't
+ # know why, disabling the optimization works, so just do
+ # that for now.
+
+ Core.need_one_cycle_delay = any(core.block_memory for core in cores)
args.verilog.write(createModule_template.format(
addrs = "".join(core.createAddr() for core in cores),
@@ -170,7 +177,7 @@ class Core(object):
# Class variable recording whether we need a one-cycle delay to
# compensate for block memories.
- need_one_cycle_delay = False
+ need_one_cycle_delay = True
def __init__(self, name):
self.name = name
diff --git a/config/core_selector.v b/config/core_selector.v
index 0f60771..3c0a31f 100644
--- a/config/core_selector.v
+++ b/config/core_selector.v
@@ -62,6 +62,9 @@ module core_selector
.error(error_board_regs)
);
+ reg [31: 0] read_data_board_regs_reg;
+ always @(posedge sys_clk)
+ read_data_board_regs_reg <= read_data_board_regs;
//----------------------------------------------------------------
@@ -85,6 +88,9 @@ module core_selector
.error(error_comm_regs)
);
+ reg [31: 0] read_data_comm_regs_reg;
+ always @(posedge sys_clk)
+ read_data_comm_regs_reg <= read_data_comm_regs;
//----------------------------------------------------------------
@@ -108,6 +114,9 @@ module core_selector
.error(error_sha256)
);
+ reg [31: 0] read_data_sha256_reg;
+ always @(posedge sys_clk)
+ read_data_sha256_reg <= read_data_sha256;
//----------------------------------------------------------------
@@ -131,6 +140,9 @@ module core_selector
.error(error_aes)
);
+ reg [31: 0] read_data_aes_reg;
+ always @(posedge sys_clk)
+ read_data_aes_reg <= read_data_aes;
//----------------------------------------------------------------
@@ -158,6 +170,9 @@ module core_selector
.debug(debug)
);
+ reg [31: 0] read_data_trng_reg;
+ always @(posedge sys_clk)
+ read_data_trng_reg <= read_data_trng;
//----------------------------------------------------------------
@@ -180,6 +195,9 @@ module core_selector
.read_data(read_data_modexp)
);
+ reg [31: 0] read_data_modexp_reg;
+ always @(posedge sys_clk)
+ read_data_modexp_reg <= read_data_modexp;
@@ -196,52 +214,52 @@ module core_selector
case (addr_core_num)
CORE_ADDR_BOARD_REGS:
begin
- sys_read_data_mux = read_data_board_regs;
+ sys_read_data_mux = read_data_board_regs_reg;
sys_error_mux = error_board_regs;
end
CORE_ADDR_COMM_REGS:
begin
- sys_read_data_mux = read_data_comm_regs;
+ sys_read_data_mux = read_data_comm_regs_reg;
sys_error_mux = error_comm_regs;
end
CORE_ADDR_SHA256:
begin
- sys_read_data_mux = read_data_sha256;
+ sys_read_data_mux = read_data_sha256_reg;
sys_error_mux = error_sha256;
end
CORE_ADDR_AES:
begin
- sys_read_data_mux = read_data_aes;
+ sys_read_data_mux = read_data_aes_reg;
sys_error_mux = error_aes;
end
CORE_ADDR_TRNG:
begin
- sys_read_data_mux = read_data_trng;
+ sys_read_data_mux = read_data_trng_reg;
sys_error_mux = error_trng;
end
CORE_ADDR_AVALANCHE_ENTROPY:
begin
- sys_read_data_mux = read_data_trng;
+ sys_read_data_mux = read_data_trng_reg;
sys_error_mux = error_trng;
end
CORE_ADDR_ROSC_ENTROPY:
begin
- sys_read_data_mux = read_data_trng;
+ sys_read_data_mux = read_data_trng_reg;
sys_error_mux = error_trng;
end
CORE_ADDR_TRNG_MIXER:
begin
- sys_read_data_mux = read_data_trng;
+ sys_read_data_mux = read_data_trng_reg;
sys_error_mux = error_trng;
end
CORE_ADDR_TRNG_CSPRNG:
begin
- sys_read_data_mux = read_data_trng;
+ sys_read_data_mux = read_data_trng_reg;
sys_error_mux = error_trng;
end
CORE_ADDR_MODEXP:
begin
- sys_read_data_mux = read_data_modexp;
+ sys_read_data_mux = read_data_modexp_reg;
sys_error_mux = 0;
end