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-rw-r--r--config/config.cfg91
-rwxr-xr-xconfig/config.py38
2 files changed, 119 insertions, 10 deletions
diff --git a/config/config.cfg b/config/config.cfg
index 65659f7..8749b55 100644
--- a/config/config.cfg
+++ b/config/config.cfg
@@ -1,7 +1,19 @@
# Config file for the Cryptech Novena FPGA framework.
+#
+# At present, there are three kinds of variables in this file.
+#
+# default-section: Name of the configuration to build if the user
+# doesn't specify one. Only meaningful in the default section.
+#
+# cores: A list of cores to build. Use with the --section option.
+#
+# vfiles: A list of Verilog files to include in the vfiles list when
+# including a particular core. All (optional) cores must have a
+# vfiles option, so that the configuration program knows what to put
+# into core_vfiles.mk.
[default]
-default = rsa
+default-section = rsa
[hash-only]
cores = sha1 sha256 sha512
@@ -17,3 +29,80 @@ cores = sha256 aes trng modexp
[multi-test]
cores = sha256 aes aes chacha aes
+
+[sha1]
+vfiles =
+ hash/sha1/src/rtl/sha1.v
+ hash/sha1/src/rtl/sha1_core.v
+ hash/sha1/src/rtl/sha1_w_mem.v
+
+[sha256]
+vfiles =
+ hash/sha256/src/rtl/sha256.v
+ hash/sha256/src/rtl/sha256_core.v
+ hash/sha256/src/rtl/sha256_k_constants.v
+ hash/sha256/src/rtl/sha256_w_mem.v
+
+[sha512]
+vfiles =
+ hash/sha512/src/rtl/sha512.v
+ hash/sha512/src/rtl/sha512_core.v
+ hash/sha512/src/rtl/sha512_h_constants.v
+ hash/sha512/src/rtl/sha512_k_constants.v
+ hash/sha512/src/rtl/sha512_w_mem.v
+
+[trng]
+vfiles =
+ rng/avalanche_entropy/src/rtl/avalanche_entropy.v
+ rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v
+ rng/rosc_entropy/src/rtl/rosc.v
+ rng/rosc_entropy/src/rtl/rosc_entropy.v
+ rng/rosc_entropy/src/rtl/rosc_entropy_core.v
+ rng/trng/src/rtl/trng.v
+ rng/trng/src/rtl/trng_csprng.v
+ rng/trng/src/rtl/trng_csprng_fifo.v
+ rng/trng/src/rtl/trng_mixer.v
+
+[aes]
+vfiles =
+ cipher/aes/src/rtl/aes.v
+ cipher/aes/src/rtl/aes_core.v
+ cipher/aes/src/rtl/aes_decipher_block.v
+ cipher/aes/src/rtl/aes_encipher_block.v
+ cipher/aes/src/rtl/aes_inv_sbox.v
+ cipher/aes/src/rtl/aes_key_mem.v
+ cipher/aes/src/rtl/aes_sbox.v
+
+[chacha]
+vfiles =
+ cipher/chacha/src/rtl/chacha.v
+ cipher/chacha/src/rtl/chacha_core.v
+ cipher/chacha/src/rtl/chacha_qr.v
+
+[modexps6]
+vfiles =
+ math/modexps6/src/rtl/modexps6_adder64_carry32.v
+ math/modexps6/src/rtl/modexps6_buffer_core.v
+ math/modexps6/src/rtl/modexps6_buffer_user.v
+ math/modexps6/src/rtl/modexps6_modinv32.v
+ math/modexps6/src/rtl/modexps6_montgomery_coeff.v
+ math/modexps6/src/rtl/modexps6_montgomery_multiplier.v
+ math/modexps6/src/rtl/modexps6_top.v
+ math/modexps6/src/rtl/modexps6_wrapper.v
+ math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v
+ math/modexps6/src/rtl/ipcore/multiplier_s6.v
+ math/modexps6/src/rtl/ipcore/subtractor_s6.v
+
+[modexp]
+vfiles =
+ math/modexp/src/rtl/adder32.v
+ math/modexp/src/rtl/blockmem1r1w.v
+ math/modexp/src/rtl/blockmem2r1wptr.v
+ math/modexp/src/rtl/blockmem2r1w.v
+ math/modexp/src/rtl/blockmem2rptr1w.v
+ math/modexp/src/rtl/modexp.v
+ math/modexp/src/rtl/modexp_core.v
+ math/modexp/src/rtl/montprod.v
+ math/modexp/src/rtl/residue.v
+ math/modexp/src/rtl/shl32.v
+ math/modexp/src/rtl/shr32.v
diff --git a/config/config.py b/config/config.py
index 74a9007..6a5e532 100755
--- a/config/config.py
+++ b/config/config.py
@@ -13,34 +13,41 @@ def main():
from sys import exit
parser = ArgumentParser(description = __doc__, formatter_class = ArgumentDefaultsHelpFormatter)
- parser.add_argument("-c", "--config", help = "config file", default = "config.cfg", type = FileType("r"))
parser.add_argument("-d", "--debug", help = "enable debugging", action = "store_true")
- parser.add_argument("-o", "--outfile", help = "output file", default = "core_selector.v", type = FileType("w"))
parser.add_argument("-s", "--section", help = "config file section")
+ parser.add_argument("-c", "--config", help = "configuration file", default = "config.cfg", type = FileType("r"))
+ parser.add_argument("--verilog", help = "verilog output file", default = "core_selector.v", type = FileType("w"))
+ parser.add_argument("--makefile", help = "output makefile", default = "core_vfiles.mk", type = FileType("w"))
parser.add_argument("core", help = "name(s) of core(s)", nargs = "*")
args = parser.parse_args()
try:
+ cfg = RawConfigParser()
+ cfg.readfp(args.config)
+
if args.core:
cores = args.core
else:
- cfg = RawConfigParser()
- cfg.readfp(args.config)
- section = args.section or cfg.get("default", "default")
+ section = args.section or cfg.get("default", "default-section")
cores = cfg.get(section, "cores").split()
cores.insert(0, "board_regs")
cores.insert(1, "comm_regs")
- cores = [Core.new(core) for core in cores]
+ cores = tuple(Core.new(core) for core in cores)
core_number = 0
for core in cores:
core_number = core.assign_core_number(core_number)
+ for core in cores[2:]:
+ core.add_vfiles(cfg)
- args.outfile.write(createModule_template.format(
- addrs = "".join(core.createAddr() for core in cores),
+ args.verilog.write(createModule_template.format(
+ addrs = "".join(core.createAddr() for core in cores),
insts = "".join(core.createInstance() for core in cores),
- muxes = "".join(core.createMux() for core in cores)))
+ muxes = "".join(core.createMux() for core in cores)))
+
+ args.makefile.write(listVfiles_template.format(
+ vfiles = "".join(core.listVfiles() for core in cores)))
except Exception, e:
if args.debug:
@@ -67,6 +74,7 @@ class Core(object):
def __init__(self, name):
self.name = name
self.core_number = None
+ self.vfiles = ()
self.instance_number = self._instance_count.get(name, 0)
self._instance_count[name] = self.instance_number + 1
@@ -78,6 +86,10 @@ class Core(object):
self.core_number = n
return n + 1
+ def add_vfiles(self, cfg):
+ if self.instance_number == 0:
+ self.vfiles = cfg.get(self.name, "vfiles").split()
+
@property
def instance_name(self):
if self._instance_count[self.name] > 1:
@@ -98,6 +110,8 @@ class Core(object):
def createMux(self):
return createMux_template.format(core = self, core0 = self)
+ def listVfiles(self):
+ return "".join(" \\\n\t$(core_tree)/" + vfile for vfile in self.vfiles)
class SubCore(Core):
""""
@@ -290,6 +304,12 @@ endmodule
//======================================================================
"""
+# Template for makefile snippet listing Verilog source files.
+
+listVfiles_template = """\
+vfiles +={vfiles}
+"""
+
# Run main program.
if __name__ == "__main__":