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-rwxr-xr-xconfig/config.py52
-rw-r--r--config/core_selector.v12
2 files changed, 50 insertions, 14 deletions
diff --git a/config/config.py b/config/config.py
index c0c3c5e..3cb69db 100755
--- a/config/config.py
+++ b/config/config.py
@@ -36,6 +36,32 @@ Generate core_selector.v and core_vfiles.mk for a set of cores.
# two-level (no segment) scheme and handle modexps6 as a set of four
# contiguous "cores" with a 10-bit composite register selector.
+# Gah: the TRNG core's internal multiplexer doesn't allocate cores
+# contiguously, there's a gap, and one just has to know what the
+# offsets are. So we need to adjust for all of that. Feh. In theory
+# we could hide the gap from the outside world, as it's just a matter
+# of (magic) constant offsets on top of the ones we're already
+# fiddling with in the core_selector mux. See
+# core/rng/trng/src/rtl/trng.v for the authoritative list, but the
+# magic offsets for the high 4 bits of the 12-bit TRNG address are:
+#
+# 0: trng
+# 1: -
+# 2: -
+# 3: -
+# 4: -
+# 5: entropy1 (avalanche)
+# 6: entropy2 (rosc)
+# 7: -
+# 8: -
+# 9: -
+# a: mixer
+# b: csprng
+# c: -
+# d: -
+# e: -
+# f: -
+
# The modexps6 core also drags in a one clock cycle delay to other
# cores, to compensate for the extra clock cycle consumed by the block
# memories used in the modexps6 core.
@@ -217,23 +243,33 @@ class SubCore(Core):
class TRNGCore(Core):
"""
- The TRNG core has an internal mux and a collection of sub-cores.
+ The TRNG core has an internal mux with slots for 15 sub-cores,
+ most of which are empty. This is a bit of a mess.
+
Mostly this means that our method calls have to iterate over all
of the subcores after handling the base TRNG core, but we also use
- a different instance template in the hope that it is easier to read.
+ different templates, and fiddle with addresses a bit.
+
+ Mux numbers have to be dug out of the TRNG Verilog source.
"""
- subcore_names = ("avalanche_entropy", "rosc_entropy", "trng_mixer", "trng_csprng")
+ # TRNG subcore name -> internal mux number.
+ subcore_parameters = dict(avalanche_entropy = 0x5,
+ rosc_entropy = 0x6,
+ trng_mixer = 0xa,
+ trng_csprng = 0xb)
def __init__(self, name):
super(TRNGCore, self).__init__(name)
- self.subcores = tuple(SubCore(name, self) for name in self.subcore_names)
+ self.subcores = tuple(SubCore(name, self)
+ for name in sorted(self.subcore_parameters,
+ key = lambda x: self.subcore_parameters[x]))
def assign_core_number(self, n):
n = super(TRNGCore, self).assign_core_number(n)
for subcore in self.subcores:
- n = subcore.assign_core_number(n)
- return n
+ subcore.assign_core_number(self.core_number + self.subcore_parameters[subcore.name])
+ return n + 15
@property
def last_subcore_upper_instance_name(self):
@@ -323,7 +359,7 @@ createInstance_template_ModExpS6 = """\
//----------------------------------------------------------------
// {core.upper_instance_name}
//----------------------------------------------------------------
- wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 3);
+ wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 9'h03);
wire [31: 0] read_data_{core.instance_name};
wire [1:0] {core.instance_name}_prefix = addr_core_num[1:0] - CORE_ADDR_{core.upper_instance_name};
@@ -351,7 +387,7 @@ createInstance_template_TRNG = """\
//----------------------------------------------------------------
// {core.upper_instance_name}
//----------------------------------------------------------------
- wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.last_subcore_upper_instance_name});
+ wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 9'h0f);
wire [31: 0] read_data_{core.instance_name};
wire error_{core.instance_name};
wire [3:0] {core.instance_name}_prefix = addr_core_num[3:0] - CORE_ADDR_{core.upper_instance_name};
diff --git a/config/core_selector.v b/config/core_selector.v
index cc7ca14..90b688e 100644
--- a/config/core_selector.v
+++ b/config/core_selector.v
@@ -34,11 +34,11 @@ module core_selector
localparam CORE_ADDR_SHA256 = 9'h02;
localparam CORE_ADDR_AES = 9'h03;
localparam CORE_ADDR_TRNG = 9'h04;
- localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h05;
- localparam CORE_ADDR_ROSC_ENTROPY = 9'h06;
- localparam CORE_ADDR_TRNG_MIXER = 9'h07;
- localparam CORE_ADDR_TRNG_CSPRNG = 9'h08;
- localparam CORE_ADDR_MODEXP = 9'h09;
+ localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h09;
+ localparam CORE_ADDR_ROSC_ENTROPY = 9'h0a;
+ localparam CORE_ADDR_TRNG_MIXER = 9'h0e;
+ localparam CORE_ADDR_TRNG_CSPRNG = 9'h0f;
+ localparam CORE_ADDR_MODEXP = 9'h14;
//----------------------------------------------------------------
@@ -148,7 +148,7 @@ module core_selector
//----------------------------------------------------------------
// TRNG
//----------------------------------------------------------------
- wire enable_trng = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG_CSPRNG);
+ wire enable_trng = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG + 9'h0f);
wire [31: 0] read_data_trng;
wire error_trng;
wire [3:0] trng_prefix = addr_core_num[3:0] - CORE_ADDR_TRNG;