diff options
Diffstat (limited to 'config/config.py')
| -rwxr-xr-x | config/config.py | 30 |
1 files changed, 6 insertions, 24 deletions
diff --git a/config/config.py b/config/config.py index 0f3818f..de28e7b 100755 --- a/config/config.py +++ b/config/config.py @@ -36,19 +36,6 @@ Generate core_selector.v and core_vfiles.mk for a set of cores. # two-level (no segment) scheme and handle modexps6 as a set of four # contiguous "cores" with a 10-bit composite register selector. -# At present, TRNG core's internal multiplexer doesn't allocate cores -# contiguously, there's a gap, and one just has to know what the -# offsets are. Current theory is that we'll fix the TRNG core to get -# rid of this problem, but for now the workaround requires this script -# to know the magic offsets for the high 4 bits of the 12-bit TRNG -# address: -# -# 0x0: trng -# 0x5: entropy1 (avalanche) -# 0x6: entropy2 (rosc) -# 0xa: mixer -# 0xb: csprng - # The modexps6 core drags in a one clock cycle delay to other cores, # to compensate for the extra clock cycle consumed by the block # memories used in the modexps6 core. We probably want a general @@ -106,9 +93,6 @@ def main(): for core in cores: core_number = core.assign_core_number(core_number) - cores[0].reset_high = True - cores[1].reset_high = True - for core in cores: core.configure(cfg) @@ -183,7 +167,6 @@ class Core(object): self.name = name self.core_number = None self.vfiles = [] - self.reset_high = False self.error_wire = True self.block_memory = False self.instance_number = self._instance_count.get(name, 0) @@ -203,7 +186,6 @@ class Core(object): for required in cfg.getvalues(self.name, "requires"): if required not in self._instance_count: self.vfiles.extend(cfg.getvalues(required, "vfiles")) - self.reset_high = cfg.getboolean(self.name, "reset_high", self.reset_high) self.error_wire = cfg.getboolean(self.name, "error_wire", self.error_wire) self.block_memory = cfg.getboolean(self.name, "block_memory", self.block_memory) @@ -220,7 +202,7 @@ class Core(object): @property def reset_pin(self): - return ".rst(sys_rst)" if self.reset_high else ".reset_n(~sys_rst)" + return ".reset_n(sys_rst_n)" @property def error_port(self): @@ -277,10 +259,10 @@ class TRNGCore(Core): """ # TRNG subcore name -> internal mux number. - subcore_parameters = dict(avalanche_entropy = 0x5, - rosc_entropy = 0x6, - trng_mixer = 0xa, - trng_csprng = 0xb) + subcore_parameters = dict(avalanche_entropy = 0x1, + rosc_entropy = 0x2, + trng_mixer = 0x3, + trng_csprng = 0x4) def __init__(self, name): super(TRNGCore, self).__init__(name) @@ -472,7 +454,7 @@ createModule_template = """\ module core_selector ( input wire sys_clk, - input wire sys_rst, + input wire sys_rst_n, input wire [16: 0] sys_eim_addr, input wire sys_eim_wr, |