1 files changed, 64 insertions, 0 deletions
diff --git a/common/rtl/lint-dummy.v b/common/rtl/lint-dummy.v
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+// dummy modules for Xilinx IP for verilator linting
+
+// The module definitions are ganked from
+// /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims. It would be easier
+// to run verilator with -I for that directory, but verilator really
+// doesn't like the Xilinx code.
+
+/*verilator lint_off UNDRIVEN*/
+/*verilator lint_off UNUSED*/
+
+module DCM_SP (
+	CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90,
+	CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS,
+	CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
+parameter real CLKDV_DIVIDE = 2.0;
+parameter integer CLKFX_DIVIDE = 1;
+parameter integer CLKFX_MULTIPLY = 4;
+parameter CLKIN_DIVIDE_BY_2 = "FALSE";
+parameter real CLKIN_PERIOD = 10.0;
+parameter CLKOUT_PHASE_SHIFT = "NONE";
+parameter CLK_FEEDBACK = "1X";
+parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+parameter DFS_FREQUENCY_MODE = "LOW";
+parameter DLL_FREQUENCY_MODE = "LOW";
+parameter DSS_MODE = "NONE";
+parameter DUTY_CYCLE_CORRECTION = "TRUE";
+parameter FACTORY_JF = 16'hC080;
+parameter integer PHASE_SHIFT = 0;
+parameter STARTUP_WAIT = "FALSE";
+output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
+output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
+output [7:0] STATUS;
+input CLKFB, CLKIN, DSSEN;
+input PSCLK, PSEN, PSINCDEC, RST;
+endmodule
+
+module BUFG (O, I);
+    output O;
+    input  I;
+endmodule
+
+module IBUFGDS (O, I, IB);
+    output O;
+    input  I, IB;
+endmodule
+
+module IOBUF (O, IO, I, T);
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter integer DRIVE = 12;
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IFD_DELAY_VALUE = "AUTO";
+    parameter IOSTANDARD = "DEFAULT";
+    parameter SLEW = "SLOW";
+    output O;
+    inout  IO;
+    input  I, T;
+endmodule
+
+module FDCE (Q, C, CE, CLR, D);
+    parameter INIT = 1'b0;
+    output Q;
+    input  C, CE, CLR, D;
+endmodule