2 files changed, 65 insertions, 0 deletions
diff --git a/common/rtl/ipcore/clkmgr_dcm.v b/common/rtl/ipcore/clkmgr_dcm.v
index 71477a8..6e57c3d 100644
--- a/common/rtl/ipcore/clkmgr_dcm.v
+++ b/common/rtl/ipcore/clkmgr_dcm.v
@@ -62,6 +62,10 @@
 //----------------------------------------------------------------------------
 // __primary______________50____________0.010
 
+/*verilator lint_off PINCONNECTEMPTY*/
+/*verilator lint_off UNDRIVEN*/
+/*verilator lint_off UNUSED*/
+
 `timescale 1ps/1ps
 
 (* CORE_GENERATION_INFO = "clkmgr_dcm,clk_wiz_v3_6,{component_name=clkmgr_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
diff --git a/common/rtl/lint-dummy.v b/common/rtl/lint-dummy.v
index 9016622..9d4d2d3 100644
--- a/common/rtl/lint-dummy.v
+++ b/common/rtl/lint-dummy.v
@@ -62,3 +62,64 @@ module FDCE (Q, C, CE, CLR, D);
     output Q;
     input  C, CE, CLR, D;
 endmodule
+
+module FD (Q, C, D);
+    parameter INIT = 1'b0;
+    output Q;
+    input  C, D;
+endmodule
+
+module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP); 
+    parameter integer A0REG = 0;
+    parameter integer A1REG = 1;
+    parameter integer B0REG = 0;
+    parameter integer B1REG = 1;
+    parameter integer CARRYINREG = 1;
+    parameter integer CARRYOUTREG = 1;
+    parameter CARRYINSEL = "OPMODE5";
+    parameter integer CREG = 1;
+    parameter integer DREG = 1;
+    parameter integer MREG = 1;
+    parameter integer OPMODEREG = 1;
+    parameter integer PREG = 1;
+    parameter RSTTYPE = "SYNC";
+    output [17:0] BCOUT; 
+    output CARRYOUT; 
+    output CARRYOUTF; 
+    output [35:0] M; 
+    output [47:0] P; 
+    output [47:0] PCOUT;
+    input [17:0] A;
+    input [17:0] B;
+    input [47:0] C;
+    input CARRYIN;
+    input CEA;
+    input CEB;
+    input CEC;
+    input CECARRYIN;
+    input CED;
+    input CEM;
+    input CEOPMODE;
+    input CEP;
+    input CLK;
+    input [17:0] D;
+    input [7:0] OPMODE;
+    input [47:0] PCIN;
+    input RSTA;
+    input RSTB;
+    input RSTC;
+    input RSTCARRYIN;
+    input RSTD;
+    input RSTM;  
+    input RSTOPMODE;
+    input RSTP;
+endmodule
+
+module GND(G);
+    output G;
+endmodule
+
+module VCC(P);
+    output P;
+endmodule
+