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-rw-r--r--common/rtl/clkmgr_dcm.v147
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.v152
-rw-r--r--common/rtl/novena_clkmgr.v53
-rw-r--r--common/rtl/novena_regs.v6
4 files changed, 182 insertions, 176 deletions
diff --git a/common/rtl/clkmgr_dcm.v b/common/rtl/clkmgr_dcm.v
new file mode 100644
index 0000000..7c851f1
--- /dev/null
+++ b/common/rtl/clkmgr_dcm.v
@@ -0,0 +1,147 @@
+//======================================================================
+//
+// clkmgr_dcm.v
+// ---------------
+// Xilinx DCM_SP primitive wrapper to avoid using Clocking Wizard IP core.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module clkmgr_dcm
+ (
+ input wire clk_in,
+ input wire reset_in,
+
+ output wire gclk_missing_out,
+
+ output wire clk_out,
+ output wire clk_valid_out
+ );
+
+
+ //
+ // Parameters
+ //
+ parameter CLK_OUT_MUL = 2; // multiply factor for output clock frequency (2..32)
+ parameter CLK_OUT_DIV = 2; // divide factor for output clock frequency (1..32)
+
+
+ //
+ // DCM_SP
+ //
+ /* Xilinx-specific primitive. */
+ wire dcm_clk_0;
+ wire dcm_clk_feedback;
+ wire dcm_clk_fx;
+ wire dcm_locked_int;
+ wire [ 7: 0] dcm_status_int;
+
+ DCM_SP #
+ (
+ .STARTUP_WAIT ("FALSE"),
+ .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
+ .CLK_FEEDBACK ("1X"),
+
+ .PHASE_SHIFT (0),
+ .CLKOUT_PHASE_SHIFT ("NONE"),
+
+ .CLKIN_PERIOD (20.0), // 50 MHz => 20 ns
+ .CLKIN_DIVIDE_BY_2 ("FALSE"),
+
+ .CLKDV_DIVIDE (5.000),
+ .CLKFX_MULTIPLY (CLK_OUT_MUL),
+ .CLKFX_DIVIDE (CLK_OUT_DIV)
+ )
+ DCM_SP_inst
+ (
+ .RST (reset_in),
+
+ .CLKIN (clk_in),
+ .CLKFB (dcm_clk_feedback),
+ .CLKDV (),
+
+ .CLK0 (dcm_clk_0),
+ .CLK90 (),
+ .CLK180 (),
+ .CLK270 (),
+
+ .CLK2X (),
+ .CLK2X180 (),
+
+ .CLKFX (dcm_clk_fx),
+ .CLKFX180 (),
+
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (),
+
+ .LOCKED (dcm_locked_int),
+ .STATUS (dcm_status_int),
+
+ .DSSEN (1'b0)
+ );
+
+
+ //
+ // Mapping
+ //
+ assign gclk_missing_out= dcm_status_int[1];
+ assign clk_valid_out = dcm_locked_int & ((dcm_status_int[2:1] == 2'b00) ? 1'b1 : 1'b0);
+
+
+ //
+ // Feedback
+ //
+ /* DCM_SP requires BUFG primitive in its feedback path. */
+ BUFG BUFG_feedback
+ (
+ .I (dcm_clk_0),
+ .O (dcm_clk_feedback)
+ );
+
+ //
+ // Output Buffer
+ //
+ /* Connect system clock to global clocking network. */
+ BUFG BUFG_output
+ (
+ .I (dcm_clk_fx),
+ .O (clk_out)
+ );
+
+
+endmodule
+
+//======================================================================
+// EOF clkmgr_dcm.v
+//======================================================================
diff --git a/common/rtl/ipcore/clkmgr_dcm.v b/common/rtl/ipcore/clkmgr_dcm.v
deleted file mode 100644
index 6e57c3d..0000000
--- a/common/rtl/ipcore/clkmgr_dcm.v
+++ /dev/null
@@ -1,152 +0,0 @@
-// file: clkmgr_dcm.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-//----------------------------------------------------------------------------
-// User entered comments
-//----------------------------------------------------------------------------
-// None
-//
-//----------------------------------------------------------------------------
-// "Output Output Phase Duty Pk-to-Pk Phase"
-// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
-//----------------------------------------------------------------------------
-// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
-//
-//----------------------------------------------------------------------------
-// "Input Clock Freq (MHz) Input Jitter (UI)"
-//----------------------------------------------------------------------------
-// __primary______________50____________0.010
-
-/*verilator lint_off PINCONNECTEMPTY*/
-/*verilator lint_off UNDRIVEN*/
-/*verilator lint_off UNUSED*/
-
-`timescale 1ps/1ps
-
-(* CORE_GENERATION_INFO = "clkmgr_dcm,clk_wiz_v3_6,{component_name=clkmgr_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
-module clkmgr_dcm
- (// Clock in ports
- input CLK_IN1,
- // Clock out ports
- output CLK_OUT1,
- // Status and control signals
- input RESET,
- output INPUT_CLK_STOPPED,
- output CLK_VALID
- );
-
- // Input buffering
- //------------------------------------
- assign clkin1 = CLK_IN1;
-
-
- // Clocking primitive
- //------------------------------------
-
- // Instantiation of the DCM primitive
- // * Unused inputs are tied off
- // * Unused outputs are labeled unused
- wire psdone_unused;
- wire locked_int;
- wire [7:0] status_int;
- wire clkfb;
- wire clk0;
-
- DCM_SP
- #(.CLKDV_DIVIDE (2.000),
- .CLKFX_DIVIDE (1),
- .CLKFX_MULTIPLY (4),
- .CLKIN_DIVIDE_BY_2 ("FALSE"),
- .CLKIN_PERIOD (20.0),
- .CLKOUT_PHASE_SHIFT ("NONE"),
- .CLK_FEEDBACK ("1X"),
- .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
- .PHASE_SHIFT (0),
- .STARTUP_WAIT ("FALSE"))
- dcm_sp_inst
- // Input clock
- (.CLKIN (clkin1),
- .CLKFB (clkfb),
- // Output clocks
- .CLK0 (clk0),
- .CLK90 (),
- .CLK180 (),
- .CLK270 (),
- .CLK2X (),
- .CLK2X180 (),
- .CLKFX (),
- .CLKFX180 (),
- .CLKDV (),
- // Ports for dynamic phase shift
- .PSCLK (1'b0),
- .PSEN (1'b0),
- .PSINCDEC (1'b0),
- .PSDONE (),
- // Other control and status signals
- .LOCKED (locked_int),
- .STATUS (status_int),
-
- .RST (RESET),
- // Unused pin- tie low
- .DSSEN (1'b0));
-
- assign INPUT_CLK_STOPPED = status_int[1];
- assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[1] == 1'b 0 ) );
-
- // Output buffering
- //-----------------------------------
- assign clkfb = CLK_OUT1;
-
- BUFG clkout1_buf
- (.O (CLK_OUT1),
- .I (clk0));
-
-
-
-
-endmodule
diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v
index 97db451..e8ef1bd 100644
--- a/common/rtl/novena_clkmgr.v
+++ b/common/rtl/novena_clkmgr.v
@@ -39,19 +39,21 @@
module novena_clkmgr
(
- input wire gclk_p, // signal from clock pins
- input wire gclk_n, //
+ input wire gclk_p, // signal from clock pins
+ input wire gclk_n, //
- input wire reset_mcu_b, // cpu reset (async)
+ input wire reset_mcu_b, // cpu reset (async, active-low)
- output wire sys_clk, // buffered system clock output
- output wire sys_rst // system reset output (sync)
+ output wire sys_clk, // buffered system clock output
+ output wire sys_rst_n // system reset output (async set, sync clear, active-low)
);
+
//
- // Ports
+ // Parameters
//
-
+ parameter CLK_OUT_MUL = 2;
+ parameter CLK_OUT_DIV = 2;
//
// IBUFGDS
@@ -70,18 +72,23 @@ module novena_clkmgr
//
// DCM
//
- wire dcm_reset; // dcm reset
- wire dcm_locked; // output clock valid
+ wire dcm_reset; // dcm reset
+ wire dcm_locked; // output clock valid
wire gclk_missing; // no input clock
- clkmgr_dcm dcm
+ clkmgr_dcm #
(
- .CLK_IN1(gclk),
- .RESET(dcm_reset),
- .INPUT_CLK_STOPPED(gclk_missing),
+ .CLK_OUT_MUL (CLK_OUT_MUL),
+ .CLK_OUT_DIV (CLK_OUT_DIV)
+ )
+ dcm
+ (
+ .clk_in (gclk),
+ .reset_in (dcm_reset),
+ .gclk_missing_out (gclk_missing),
- .CLK_OUT1(sys_clk),
- .CLK_VALID(dcm_locked)
+ .clk_out (sys_clk),
+ .clk_valid_out (dcm_locked)
);
@@ -90,7 +97,8 @@ module novena_clkmgr
//
/* DCM should be reset on power-up, when input clock is stopped or when the
- * CPU gets reset.
+ * CPU gets reset. Note that DCM requires active-high reset, so the shift
+ * register is preloaded with 1's and gradually filled with 0's.
*/
reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
@@ -109,18 +117,21 @@ module novena_clkmgr
// System Reset Logic
//
- /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
+ /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note
+ * that system reset is active-low, so the shift register is preloaded with
+ * 0's and gradually filled with 1's.
+ */
- reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register
+ reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register
always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked)
//
if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0))
- sys_rst_shreg <= {16{1'b1}};
+ sys_rst_shreg <= {16{1'b0}};
else if (dcm_locked == 1'b1)
- sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0};
+ sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1};
- assign sys_rst = sys_rst_shreg[15];
+ assign sys_rst_n = sys_rst_shreg[15];
endmodule
diff --git a/common/rtl/novena_regs.v b/common/rtl/novena_regs.v
index eb89092..4edf028 100644
--- a/common/rtl/novena_regs.v
+++ b/common/rtl/novena_regs.v
@@ -42,7 +42,7 @@ module board_regs
(
// Clock and reset.
input wire clk,
- input wire rst,
+ input wire reset_n,
// Control.
input wire cs,
@@ -96,9 +96,9 @@ module board_regs
//----------------------------------------------------------------
// storage registers for mapping memory to core interface
//----------------------------------------------------------------
- always @ (posedge clk or posedge rst)
+ always @ (posedge clk or negedge reset_n)
begin
- if (rst)
+ if (!reset_n)
begin
reg_dummy <= {32{1'b0}};
end