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-rw-r--r--common/rtl/clkmgr_dcm.v7
-rw-r--r--common/rtl/novena_clkmgr.v18
2 files changed, 16 insertions, 9 deletions
diff --git a/common/rtl/clkmgr_dcm.v b/common/rtl/clkmgr_dcm.v
index 5651b93..7c851f1 100644
--- a/common/rtl/clkmgr_dcm.v
+++ b/common/rtl/clkmgr_dcm.v
@@ -51,13 +51,14 @@ module clkmgr_dcm
//
// Parameters
//
- parameter CLK_OUT_MUL = 2;
- parameter CLK_OUT_DIV = 2;
+ parameter CLK_OUT_MUL = 2; // multiply factor for output clock frequency (2..32)
+ parameter CLK_OUT_DIV = 2; // divide factor for output clock frequency (1..32)
//
// DCM_SP
//
+ /* Xilinx-specific primitive. */
wire dcm_clk_0;
wire dcm_clk_feedback;
wire dcm_clk_fx;
@@ -121,6 +122,7 @@ module clkmgr_dcm
//
// Feedback
//
+ /* DCM_SP requires BUFG primitive in its feedback path. */
BUFG BUFG_feedback
(
.I (dcm_clk_0),
@@ -130,6 +132,7 @@ module clkmgr_dcm
//
// Output Buffer
//
+ /* Connect system clock to global clocking network. */
BUFG BUFG_output
(
.I (dcm_clk_fx),
diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v
index 9151e93..e8ef1bd 100644
--- a/common/rtl/novena_clkmgr.v
+++ b/common/rtl/novena_clkmgr.v
@@ -45,7 +45,7 @@ module novena_clkmgr
input wire reset_mcu_b, // cpu reset (async, active-low)
output wire sys_clk, // buffered system clock output
- output wire sys_rst // system reset output (sync, active-high)
+ output wire sys_rst_n // system reset output (async set, sync clear, active-low)
);
@@ -97,7 +97,8 @@ module novena_clkmgr
//
/* DCM should be reset on power-up, when input clock is stopped or when the
- * CPU gets reset.
+ * CPU gets reset. Note that DCM requires active-high reset, so the shift
+ * register is preloaded with 1's and gradually filled with 0's.
*/
reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
@@ -116,18 +117,21 @@ module novena_clkmgr
// System Reset Logic
//
- /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
+ /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note
+ * that system reset is active-low, so the shift register is preloaded with
+ * 0's and gradually filled with 1's.
+ */
- reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register
+ reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register
always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked)
//
if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0))
- sys_rst_shreg <= {16{1'b1}};
+ sys_rst_shreg <= {16{1'b0}};
else if (dcm_locked == 1'b1)
- sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0};
+ sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1};
- assign sys_rst = sys_rst_shreg[15];
+ assign sys_rst_n = sys_rst_shreg[15];
endmodule