diff options
Diffstat (limited to 'common/rtl/novena_clkmgr.v')
| -rw-r--r-- | common/rtl/novena_clkmgr.v | 53 |
1 files changed, 32 insertions, 21 deletions
diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v index 97db451..e8ef1bd 100644 --- a/common/rtl/novena_clkmgr.v +++ b/common/rtl/novena_clkmgr.v @@ -39,19 +39,21 @@ module novena_clkmgr ( - input wire gclk_p, // signal from clock pins - input wire gclk_n, // + input wire gclk_p, // signal from clock pins + input wire gclk_n, // - input wire reset_mcu_b, // cpu reset (async) + input wire reset_mcu_b, // cpu reset (async, active-low) - output wire sys_clk, // buffered system clock output - output wire sys_rst // system reset output (sync) + output wire sys_clk, // buffered system clock output + output wire sys_rst_n // system reset output (async set, sync clear, active-low) ); + // - // Ports + // Parameters // - + parameter CLK_OUT_MUL = 2; + parameter CLK_OUT_DIV = 2; // // IBUFGDS @@ -70,18 +72,23 @@ module novena_clkmgr // // DCM // - wire dcm_reset; // dcm reset - wire dcm_locked; // output clock valid + wire dcm_reset; // dcm reset + wire dcm_locked; // output clock valid wire gclk_missing; // no input clock - clkmgr_dcm dcm + clkmgr_dcm # ( - .CLK_IN1(gclk), - .RESET(dcm_reset), - .INPUT_CLK_STOPPED(gclk_missing), + .CLK_OUT_MUL (CLK_OUT_MUL), + .CLK_OUT_DIV (CLK_OUT_DIV) + ) + dcm + ( + .clk_in (gclk), + .reset_in (dcm_reset), + .gclk_missing_out (gclk_missing), - .CLK_OUT1(sys_clk), - .CLK_VALID(dcm_locked) + .clk_out (sys_clk), + .clk_valid_out (dcm_locked) ); @@ -90,7 +97,8 @@ module novena_clkmgr // /* DCM should be reset on power-up, when input clock is stopped or when the - * CPU gets reset. + * CPU gets reset. Note that DCM requires active-high reset, so the shift + * register is preloaded with 1's and gradually filled with 0's. */ reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register @@ -109,18 +117,21 @@ module novena_clkmgr // System Reset Logic // - /* System reset is asserted for 16 cycles whenever DCM aquires lock. */ + /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note + * that system reset is active-low, so the shift register is preloaded with + * 0's and gradually filled with 1's. + */ - reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register + reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) // if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) - sys_rst_shreg <= {16{1'b1}}; + sys_rst_shreg <= {16{1'b0}}; else if (dcm_locked == 1'b1) - sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; + sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1}; - assign sys_rst = sys_rst_shreg[15]; + assign sys_rst_n = sys_rst_shreg[15]; endmodule |