diff options
Diffstat (limited to 'common/rtl/ipcore/clkmgr_dcm')
42 files changed, 0 insertions, 2842 deletions
diff --git a/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt b/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt deleted file mode 100644 index 91dcdd0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt +++ /dev/null @@ -1,184 +0,0 @@ -CHANGE LOG for LogiCORE Clocking Wizard V3.6 - - Release Date: June 19, 2013 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ - -................................................................................ - -2. DEVICE SUPPORT - - - 2.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - Spread Spectrum support for 7 series MMCME2 - - - ISE 14.2 software support - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - Resolved issue with example design becoming core top in planAhead - - Resolved issue with Virtex6 MMCM instantiation for VHDL project - Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm - -................................................................................ - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - - -................................................................................ - -6. TECHNICAL SUPPORT & FEEDBACK - - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support -10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support -07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt deleted file mode 100644 index 91dcdd0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt +++ /dev/null @@ -1,184 +0,0 @@ -CHANGE LOG for LogiCORE Clocking Wizard V3.6 - - Release Date: June 19, 2013 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ - -................................................................................ - -2. DEVICE SUPPORT - - - 2.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - Spread Spectrum support for 7 series MMCME2 - - - ISE 14.2 software support - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - Resolved issue with example design becoming core top in planAhead - - Resolved issue with Virtex6 MMCM instantiation for VHDL project - Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm - -................................................................................ - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - - -................................................................................ - -6. TECHNICAL SUPPORT & FEEDBACK - - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support -10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support -07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html deleted file mode 100644 index d6deba0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html +++ /dev/null @@ -1,195 +0,0 @@ -<HTML> -<HEAD> -<TITLE>clk_wiz_v3_6_vinfo</TITLE> -<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> -</HEAD> -<BODY> -<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> -CHANGE LOG for LogiCORE Clocking Wizard V3.6 - - Release Date: June 19, 2013 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> - -For system requirements: - - <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 -solution. For the latest core updates, see the product page at: - - <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A> - -................................................................................ - -2. DEVICE SUPPORT - - - 2.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - Spread Spectrum support for 7 series MMCME2 - - - ISE 14.2 software support - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - Resolved issue with example design becoming core top in planAhead - - Resolved issue with Virtex6 MMCM instantiation for VHDL project - Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A> - -................................................................................ - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> - - -................................................................................ - -6. TECHNICAL SUPPORT & FEEDBACK - - -To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support -10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support -07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - -</FONT> -</PRE> -</BODY> -</HTML> diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf b/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf Binary files differdeleted file mode 100644 index a7daa60..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf +++ /dev/null diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf deleted file mode 100644 index dffb528..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf +++ /dev/null @@ -1,60 +0,0 @@ -# file: clkmgr_dcm_exdes.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
-
-
-# FALSE PATH constraints
-PIN "COUNTER_RESET" TIG;
-PIN "RESET" TIG;
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v deleted file mode 100644 index 10627b3..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v +++ /dev/null @@ -1,164 +0,0 @@ -// file: clkmgr_dcm_exdes.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard example design
-//----------------------------------------------------------------------------
-// This example design instantiates the created clocking network, where each
-// output clock drives a counter. The high bit of each counter is ported.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-module clkmgr_dcm_exdes
- #(
- parameter TCQ = 100
- )
- (// Clock in ports
- input CLK_IN1,
- // Reset that only drives logic in example design
- input COUNTER_RESET,
- output [1:1] CLK_OUT,
- // High bits of counters driven by clocks
- output COUNT,
- // Status and control signals
- input RESET,
- output INPUT_CLK_STOPPED,
- output CLK_VALID
- );
-
- // Parameters for the counters
- //-------------------------------
- // Counter width
- localparam C_W = 16;
- // Create reset for the counters
- wire reset_int = RESET || COUNTER_RESET;
-
- reg rst_sync;
- reg rst_sync_int;
- reg rst_sync_int1;
- reg rst_sync_int2;
-
-
-
- // Declare the clocks and counter
- wire clk_int;
- wire clk_n;
- wire clk;
- reg [C_W-1:0] counter;
-
- // Insert BUFGs on all input clocks that don't already have them
- //--------------------------------------------------------------
- BUFG clkin1_buf
- (.O (clk_in1_buf),
- .I (CLK_IN1));
-
- // Instantiation of the clocking network
- //--------------------------------------
- clkmgr_dcm clknetwork
- (// Clock in ports
- .CLK_IN1 (clk_in1_buf),
- // Clock out ports
- .CLK_OUT1 (clk_int),
- // Status and control signals
- .RESET (RESET),
- .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
- .CLK_VALID (CLK_VALID));
-
- assign clk_n = ~clk;
-
- ODDR2 clkout_oddr
- (.Q (CLK_OUT[1]),
- .C0 (clk),
- .C1 (clk_n),
- .CE (1'b1),
- .D0 (1'b1),
- .D1 (1'b0),
- .R (1'b0),
- .S (1'b0));
-
- // Connect the output clocks to the design
- //-----------------------------------------
- assign clk = clk_int;
-
-
- // Reset synchronizer
- //-----------------------------------
- always @(posedge reset_int or posedge clk) begin
- if (reset_int) begin
- rst_sync <= 1'b1;
- rst_sync_int <= 1'b1;
- rst_sync_int1 <= 1'b1;
- rst_sync_int2 <= 1'b1;
- end
- else begin
- rst_sync <= 1'b0;
- rst_sync_int <= rst_sync;
- rst_sync_int1 <= rst_sync_int;
- rst_sync_int2 <= rst_sync_int1;
- end
- end
-
-
- // Output clock sampling
- //-----------------------------------
- always @(posedge clk or posedge rst_sync_int2) begin
- if (rst_sync_int2) begin
- counter <= #TCQ { C_W { 1'b 0 } };
- end else begin
- counter <= #TCQ counter + 1'b 1;
- end
- end
-
- // alias the high bit to the output
- assign COUNT = counter[C_W-1];
-
-
-
-endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc deleted file mode 100644 index 787023d..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc +++ /dev/null @@ -1,69 +0,0 @@ -# file: clkmgr_dcm_exdes.xdc
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
-set_propagated_clock CLK_IN1
-set_input_jitter CLK_IN1 0.2
-
-# FALSE PATH constraint added on COUNTER_RESET
-set_false_path -from [get_ports "COUNTER_RESET"]
-set_false_path -from [get_ports "RESET"]
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat b/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat deleted file mode 100644 index 3d313d5..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat +++ /dev/null @@ -1,90 +0,0 @@ -REM file: implement.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM -----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the clocking wizard
-REM -----------------------------------------------------------------------------
-
-REM Clean up the results directory
-rmdir /S /Q results
-mkdir results
-
-REM Copy unisim_comp.v file to results directory
-copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
-
-REM Synthesize the Verilog Wrapper Files
-echo 'Synthesizing Clocking Wizard design with XST'
-xst -ifn xst.scr
-move clkmgr_dcm_exdes.ngc results\
-
-REM Copy the constraints files generated by Coregen
-echo 'Copying files from constraints directory to results directory'
-copy ..\example_design\clkmgr_dcm_exdes.ucf results\
-
-cd results
-
-echo 'Running ngdbuild'
-ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
-
-echo 'Running map'
-map -timing -pr b clkmgr_dcm_exdes -o mapped.ncd
-
-echo 'Running par'
-par -w mapped.ncd routed mapped.pcf
-
-echo 'Running trce'
-trce -e 10 routed -o routed mapped.pcf
-
-echo 'Running design through bitgen'
-bitgen -w routed
-
-echo 'Running netgen to create gate level model for the clocking wizard example design'
-netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
-cd ..
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh b/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh deleted file mode 100644 index 2c64bee..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh +++ /dev/null @@ -1,91 +0,0 @@ -#!/bin/sh
-# file: implement.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the clocking wizard
-#-----------------------------------------------------------------------------
-
-# Clean up the results directory
-rm -rf results
-mkdir results
-
-# Copy unisim_comp.v file to results directory
-cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
-
-# Synthesize the Verilog Wrapper Files
-echo 'Synthesizing Clocking Wizard design with XST'
-xst -ifn xst.scr
-mv clkmgr_dcm_exdes.ngc results/
-
-# Copy the constraints files generated by Coregen
-echo 'Copying files from constraints directory to results directory'
-cp ../example_design/clkmgr_dcm_exdes.ucf results/
-
-cd results
-
-echo 'Running ngdbuild'
-ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
-
-echo 'Running map'
-map -timing clkmgr_dcm_exdes -o mapped.ncd
-
-echo 'Running par'
-par -w mapped.ncd routed mapped.pcf
-
-echo 'Running trce'
-trce -e 10 routed -o routed mapped.pcf
-
-echo 'Running design through bitgen'
-bitgen -w routed
-
-echo 'Running netgen to create gate level model for the clocking wizard example design'
-netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
-
-cd ..
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat deleted file mode 100644 index 9782028..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat +++ /dev/null @@ -1,58 +0,0 @@ -REM file: planAhead_ise.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM-----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the clocking wizard
-REM-----------------------------------------------------------------------------
-
-del \f results
-mkdir results
-cd results
-
-planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh deleted file mode 100644 index 7f436b6..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh +++ /dev/null @@ -1,59 +0,0 @@ -#!/bin/sh
-# file: planAhead_ise.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the clocking wizard
-#-----------------------------------------------------------------------------
-
-rm -rf results
-mkdir results
-cd results
-
-planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl deleted file mode 100644 index ab77638..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl +++ /dev/null @@ -1,78 +0,0 @@ -# file: planAhead_ise.tcl
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-set projDir [file dirname [info script]]
-set projName clkmgr_dcm
-set topName clkmgr_dcm_exdes
-set device xc6slx45csg324-3
-
-create_project $projName $projDir/results/$projName -part $device
-
-set_property design_mode RTL [get_filesets sources_1]
-
-## Source files
-#set verilogSources [glob $srcDir/*.v]
-import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.v
-import_files -fileset [get_filesets sources_1] -force -norecurse ../../../clkmgr_dcm.v
-
-
-#UCF file
-import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.ucf
-
-set_property top $topName [get_property srcset [current_run]]
-
-launch_runs -runs synth_1
-wait_on_run synth_1
-
-set_property add_step Bitgen [get_runs impl_1]
-launch_runs -runs impl_1
-wait_on_run impl_1
-
-
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat deleted file mode 100644 index 3e1e03b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat +++ /dev/null @@ -1,58 +0,0 @@ -REM file: planAhead_rdn.sh
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM-----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the XADC wizard
-REM-----------------------------------------------------------------------------
-
-del \f results
-mkdir results
-cd results
-
-planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh deleted file mode 100644 index a5adee8..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/sh
-# file: planAhead_rdn.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the XADC wizard
-#-----------------------------------------------------------------------------
-rm -rf results
-mkdir results
-cd results
-planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl deleted file mode 100644 index e8c0fdf..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl +++ /dev/null @@ -1,69 +0,0 @@ -# file : planAhead_rdn.tcl
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-set device xc6slx45csg324-3
-set projName clkmgr_dcm
-set design clkmgr_dcm
-set projDir [file dirname [info script]]
-create_project $projName $projDir/results/$projName -part $device -force
-set_property design_mode RTL [current_fileset -srcset]
-set top_module clkmgr_dcm_exdes
-set_property top clkmgr_dcm_exdes [get_property srcset [current_run]]
-add_files -norecurse {../../../clkmgr_dcm.v}
-add_files -norecurse {../../example_design/clkmgr_dcm_exdes.v}
-import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clkmgr_dcm_exdes.xdc}
-synth_design
-opt_design
-place_design
-route_design
-write_sdf -rename_top_module clkmgr_dcm_exdes -file routed.sdf
-write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clkmgr_dcm_exdes -file routed.v
-report_timing -nworst 30 -path_type full -file routed.twr
-report_drc -file report.drc
-write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj b/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj deleted file mode 100644 index cd0e0e6..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj +++ /dev/null @@ -1,2 +0,0 @@ -verilog work ../../clkmgr_dcm.v
-verilog work ../example_design/clkmgr_dcm_exdes.v
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr b/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr deleted file mode 100644 index 20d09f4..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr +++ /dev/null @@ -1,9 +0,0 @@ -run
--ifmt MIXED
--top clkmgr_dcm_exdes
--p xc6slx45-csg324-3
--ifn xst.prj
--ofn clkmgr_dcm_exdes
--keep_hierarchy soft
--equivalent_register_removal no
--max_fanout 65535
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v deleted file mode 100644 index ee24750..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v +++ /dev/null @@ -1,145 +0,0 @@ -// file: clkmgr_dcm_tb.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard demonstration testbench
-//----------------------------------------------------------------------------
-// This demonstration testbench instantiates the example design for the
-// clocking wizard. Input clocks are toggled, which cause the clocking
-// network to lock and the counters to increment.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-`define wait_lock @(posedge CLK_VALID)
-
-module clkmgr_dcm_tb ();
-
- // Clock to Q delay of 100ps
- localparam TCQ = 100;
-
-
- // timescale is 1ps/1ps
- localparam ONE_NS = 1000;
- localparam PHASE_ERR_MARGIN = 100; // 100ps
- // how many cycles to run
- localparam COUNT_PHASE = 1024;
- // we'll be using the period in many locations
- localparam time PER1 = 20.0*ONE_NS;
- localparam time PER1_1 = PER1/2;
- localparam time PER1_2 = PER1 - PER1/2;
-
- // Declare the input clock signals
- reg CLK_IN1 = 1;
-
- // The high bit of the sampling counter
- wire COUNT;
- // Status and control signals
- reg RESET = 0;
- wire INPUT_CLK_STOPPED;
- wire CLK_VALID;
- reg COUNTER_RESET = 0;
-wire [1:1] CLK_OUT;
-//Freq Check using the M & D values setting and actual Frequency generated
-
-
- // Input clock generation
- //------------------------------------
- always begin
- CLK_IN1 = #PER1_1 ~CLK_IN1;
- CLK_IN1 = #PER1_2 ~CLK_IN1;
- end
-
- // Test sequence
- reg [15*8-1:0] test_phase = "";
- initial begin
- // Set up any display statements using time to be readable
- $timeformat(-12, 2, "ps", 10);
- COUNTER_RESET = 0;
- test_phase = "reset";
- RESET = 1;
- #(PER1*6);
- RESET = 0;
- test_phase = "wait lock";
- `wait_lock;
- #(PER1*6);
- COUNTER_RESET = 1;
- #(PER1*20)
- COUNTER_RESET = 0;
-
- test_phase = "counting";
- #(PER1*COUNT_PHASE);
-
- $display("SIMULATION PASSED");
- $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
- $finish;
- end
-
- // Instantiation of the example design containing the clock
- // network and sampling counters
- //---------------------------------------------------------
- clkmgr_dcm_exdes
- #(
- .TCQ (TCQ)
- ) dut
- (// Clock in ports
- .CLK_IN1 (CLK_IN1),
- // Reset for logic in example design
- .COUNTER_RESET (COUNTER_RESET),
- .CLK_OUT (CLK_OUT),
- // High bits of the counters
- .COUNT (COUNT),
- // Status and control signals
- .RESET (RESET),
- .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
- .CLK_VALID (CLK_VALID));
-
-// Freq Check
-
-endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl deleted file mode 100644 index e19ead8..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl +++ /dev/null @@ -1,8 +0,0 @@ -# file: simcmds.tcl
-
-# create the simulation script
-vcd dumpfile isim.vcd
-vcd dumpvars -m /clkmgr_dcm_tb -l 0
-wave add /
-run 50000ns
-quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat deleted file mode 100644 index 80904cb..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_isim.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-vlogcomp -work work %XILINX%\verilog\src\glbl.v
-vlogcomp -work work ..\..\..\clkmgr_dcm.v
-vlogcomp -work work ..\..\example_design\clkmgr_dcm_exdes.v
-vlogcomp -work work ..\clkmgr_dcm_tb.v
-
-REM compile the project
-fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
-
-REM run the simulation script
-.\clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh deleted file mode 100644 index 9fb5029..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh +++ /dev/null @@ -1,61 +0,0 @@ -# file: simulate_isim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# nt
-# create the project
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../../clkmgr_dcm.v
-vlogcomp -work work ../../example_design/clkmgr_dcm_exdes.v
-vlogcomp -work work ../clkmgr_dcm_tb.v
-
-# compile the project
-fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
-
-# run the simulation script
-./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat deleted file mode 100644 index 7497cd9..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat +++ /dev/null @@ -1,61 +0,0 @@ -REM file: simulate_mti.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM set up the working directory
-vlib work
-
-REM compile all of the files
-vlog -work work %XILINX%\verilog\src\glbl.v
-vlog -work work ..\..\..\clkmgr_dcm.v
-vlog -work work ..\..\example_design\clkmgr_dcm_exdes.v
-vlog -work work ..\clkmgr_dcm_tb.v
-
-REM run the simulation
-vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do deleted file mode 100644 index b0e526f..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $env(XILINX)/verilog/src/glbl.v
-vlog -work work ../../../clkmgr_dcm.v
-vlog -work work ../../example_design/clkmgr_dcm_exdes.v
-vlog -work work ../clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -t ps -voptargs="+acc" -L unisims_ver work.clkmgr_dcm_tb work.glbl
-do wave.do
-log clkmgr_dcm_tb/dut/counter
-log -r /*
-run 50000ns
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh deleted file mode 100644 index 66099e0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh
-# file: simulate_mti.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $XILINX/verilog/src/glbl.v
-vlog -work work ../../../clkmgr_dcm.v
-vlog -work work ../../example_design/clkmgr_dcm_exdes.v
-vlog -work work ../clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh deleted file mode 100644 index 01b0412..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh +++ /dev/null @@ -1,62 +0,0 @@ -#/bin/sh
-# file: simulate_ncsim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-mkdir work
-
-# compile all of the files
-ncvlog -work work ${XILINX}/verilog/src/glbl.v
-ncvlog -work work ../../../clkmgr_dcm.v
-ncvlog -work work ../../example_design/clkmgr_dcm_exdes.v
-ncvlog -work work ../clkmgr_dcm_tb.v
-
-# elaborate and run the simulation
-ncelab -work work -access +wc work.clkmgr_dcm_tb work.glbl
-ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.clkmgr_dcm_tb
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh deleted file mode 100644 index 39668df..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh
-# file: simulate_vcs.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# remove old files
-rm -rf simv* csrc DVEfiles AN.DB
-
-# compile all of the files
-# Note that -sverilog is not strictly required- You can
-# remove the -sverilog if you change the type of the
-# localparam for the periods in the testbench file to
-# [63:0] from time
-vlogan -sverilog \
- ${XILINX}/verilog/src/glbl.v \
- ../../../clkmgr_dcm.v \
- ../../example_design/clkmgr_dcm_exdes.v \
- ../clkmgr_dcm_tb.v
-
-# prepare the simulation
-vcs +vcs+lic+wait -debug clkmgr_dcm_tb glbl
-
-# run the simulation
-./simv -ucli -i ucli_commands.key
-
-# launch the viewer
-dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key deleted file mode 100644 index 2bbdd0f..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ -call {$vcdpluson}
-call {$vcdplusmemon(clkmgr_dcm_tb.dut.counter)}
-run
-call {$vcdplusclose}
-quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl deleted file mode 100644 index 628e55a..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,18 +0,0 @@ -gui_open_window Wave
-gui_sg_create clkmgr_dcm_group
-gui_list_add_group -id Wave.1 {clkmgr_dcm_group}
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.test_phase}
-gui_set_radix -radix {ascii} -signals {clkmgr_dcm_tb.test_phase}
-gui_sg_addsignal -group clkmgr_dcm_group {{Input_clocks}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.CLK_IN1}
-gui_sg_addsignal -group clkmgr_dcm_group {{Output_clocks}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.clk}
-gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.clk
-gui_sg_addsignal -group clkmgr_dcm_group {{Status_control}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.RESET}
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.USE_INCLK_STOPPED}
-gui_sg_addsignal -group clkmgr_dcm_group {{Counters}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.COUNT}
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.counter}
-gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.counter
-gui_zoom -window Wave.1 -full
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do deleted file mode 100644 index eee7422..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do +++ /dev/null @@ -1,60 +0,0 @@ -# file: wave.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-add wave -noupdate -format Literal -radix ascii /clkmgr_dcm_tb/test_phase
-add wave -noupdate -divider {Input clocks}
-add wave -noupdate -format Logic /clkmgr_dcm_tb/CLK_IN1
-add wave -noupdate -divider {Output clocks}
-add wave -noupdate -format Logic /clkmgr_dcm_tb/dut/clk
-add wave -noupdate -divider Status/control
-add wave -noupdate -format Logic /clkmgr_dcm_tb/RESET
-add wave -noupdate -format Logic /clkmgr_dcm_tb/INPUT_CLK_STOPPED
-add wave -noupdate -divider Counters
-add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/COUNT
-add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/dut/counter
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv deleted file mode 100644 index c3c3eef..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv +++ /dev/null @@ -1,118 +0,0 @@ -# file: wave.sv
-#
-# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# Get the windows set up
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
- window geometry "Design Browser 1" 1054x819+536+322
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set \
- -scope nc::clkmgr_dcm_tb
-browser yview see nc::clkmgr_dcm_tb
-browser timecontrol set -lock 0
-
-if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
- window geometry "Waveform 1" 1010x600+0+541
-}
-window target "Waveform 1" on
-waveform using {Waveform 1}
-waveform sidebar visibility partial
-waveform set \
- -primarycursor TimeA \
- -signalnames name \
- -signalwidth 175 \
- -units ns \
- -valuewidth 75
-cursor set -using TimeA -time 0
-waveform baseline set -time 0
-waveform xview limits 0 20000n
-
-#
-# Define signal groups
-#
-catch {group new -name {Output clocks} -overlay 0}
-catch {group new -name {Status/control} -overlay 0}
-catch {group new -name {Counters} -overlay 0}
-
-set id [waveform add -signals [list {nc::clkmgr_dcm_tb.CLK_IN1}]]
-
-group using {Output clocks}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {clkmgr_dcm_tb.dut.clk} \
-
-group using {Counters}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {clkmgr_dcm_tb.dut.counter} \
-
-group using {Status/control}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {nc::clkmgr_dcm_tb.RESET} {nc::clkmgr_dcm_tb.INPUT_CLK_STOPPED}
-
-set id [waveform add -signals [list {nc::clkmgr_dcm_tb.COUNT} ]]
-
-set id [waveform add -signals [list {nc::clkmgr_dcm_tb.test_phase} ]]
-waveform format $id -radix %a
-
-set groupId [waveform add -groups {{Input clocks}}]
-set groupId [waveform add -groups {{Output clocks}}]
-set groupId [waveform add -groups {{Status/control}}]
-set groupId [waveform add -groups {{Counters}}]
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v deleted file mode 100644 index 9618253..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v +++ /dev/null @@ -1,149 +0,0 @@ -// file: clkmgr_dcm_tb.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard demonstration testbench
-//----------------------------------------------------------------------------
-// This demonstration testbench instantiates the example design for the
-// clocking wizard. Input clocks are toggled, which cause the clocking
-// network to lock and the counters to increment.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-`define wait_lock @(posedge CLK_VALID)
-
-module clkmgr_dcm_tb ();
-
- // Clock to Q delay of 100ps
- localparam TCQ = 100;
-
-
- // timescale is 1ps/1ps
- localparam ONE_NS = 1000;
- localparam PHASE_ERR_MARGIN = 100; // 100ps
- // how many cycles to run
- localparam COUNT_PHASE = 1024;
- // we'll be using the period in many locations
- localparam time PER1 = 20.0*ONE_NS;
- localparam time PER1_1 = PER1/2;
- localparam time PER1_2 = PER1 - PER1/2;
-
- // Declare the input clock signals
- reg CLK_IN1 = 1;
-
- // The high bit of the sampling counter
- wire COUNT;
- // Status and control signals
- reg RESET = 0;
- wire INPUT_CLK_STOPPED;
- wire CLK_VALID;
- reg COUNTER_RESET = 0;
-wire [1:1] CLK_OUT;
-//Freq Check using the M & D values setting and actual Frequency generated
-
- reg [13:0] timeout_counter = 14'b00000000000000;
-
- // Input clock generation
- //------------------------------------
- always begin
- CLK_IN1 = #PER1_1 ~CLK_IN1;
- CLK_IN1 = #PER1_2 ~CLK_IN1;
- end
-
- // Test sequence
- reg [15*8-1:0] test_phase = "";
- initial begin
- // Set up any display statements using time to be readable
- $timeformat(-12, 2, "ps", 10);
- $display ("Timing checks are not valid");
- COUNTER_RESET = 0;
- test_phase = "reset";
- RESET = 1;
- #(PER1*6);
- RESET = 0;
- test_phase = "wait lock";
- `wait_lock;
- #(PER1*6);
- COUNTER_RESET = 1;
- #(PER1*19.5)
- COUNTER_RESET = 0;
- #(PER1*1)
- $display ("Timing checks are valid");
- test_phase = "counting";
- #(PER1*COUNT_PHASE);
-
- $display("SIMULATION PASSED");
- $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
- $finish;
- end
-
-
-
- // Instantiation of the example design containing the clock
- // network and sampling counters
- //---------------------------------------------------------
- clkmgr_dcm_exdes
- dut
- (// Clock in ports
- .CLK_IN1 (CLK_IN1),
- // Reset for logic in example design
- .COUNTER_RESET (COUNTER_RESET),
- .CLK_OUT (CLK_OUT),
- // High bits of the counters
- .COUNT (COUNT),
- // Status and control signals
- .RESET (RESET),
- .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
- .CLK_VALID (CLK_VALID));
-
-
-// Freq Check
-
-endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file deleted file mode 100644 index d59e315..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file +++ /dev/null @@ -1,2 +0,0 @@ -COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
-SCOPE = clkmgr_dcm_tb.dut;
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl deleted file mode 100644 index 14523af..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl +++ /dev/null @@ -1,9 +0,0 @@ -# file: simcmds.tcl
-
-# create the simulation script
-vcd dumpfile isim.vcd
-vcd dumpvars -m /clkmgr_dcm_tb -l 0
-wave add /
-run 50000ns
-quit
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh deleted file mode 100644 index 0152cb0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh +++ /dev/null @@ -1,62 +0,0 @@ -# file: simulate_isim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# create the project
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../implement/results/routed.v
-vlogcomp -work work clkmgr_dcm_tb.v
-
-# compile the project
-fuse work.clkmgr_dcm_tb work.glbl -L secureip -L simprims_ver -o clkmgr_dcm_isim.exe
-
-# run the simulation script
-./clkmgr_dcm_isim.exe -tclbatch simcmds.tcl -sdfmax /clkmgr_dcm_tb/dut=../../implement/results/routed.sdf
-
-# run the simulation script
-#./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat deleted file mode 100644 index 8a08dc0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_mti.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-# set up the working directory
-set work work
-vlib work
-
-REM compile all of the files
-vlog -work work %XILINX%\verilog\src\glbl.v
-vlog -work work ..\..\implement\results\routed.v
-vlog -work work clkmgr_dcm_tb.v
-
-REM run the simulation
-vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do deleted file mode 100644 index bfeb9c5..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $env(XILINX)/verilog/src/glbl.v
-vlog -work work ../../implement/results/routed.v
-vlog -work work clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
-#do wave.do
-#log -r /*
-run 50000ns
-
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh deleted file mode 100644 index b842adc..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh
-# file: simulate_mti.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $XILINX/verilog/src/glbl.v
-vlog -work work ../../implement/results/routed.v
-vlog -work work clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh deleted file mode 100644 index fd18dde..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh
-# file: simulate_ncsim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-mkdir work
-
-# compile all of the files
-ncvlog -work work ${XILINX}/verilog/src/glbl.v
-ncvlog -work work ../../implement/results/routed.v
-ncvlog -work work clkmgr_dcm_tb.v
-
-# elaborate and run the simulation
-ncsdfc ../../implement/results/routed.sdf
-
-ncelab -work work -access +wc -pulse_r 10 -nonotifier work.clkmgr_dcm_tb work.glbl -sdf_cmd_file sdf_cmd_file
-ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.clkmgr_dcm_tb
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh deleted file mode 100644 index 26a8c27..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh
-# file: simulate_vcs.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# remove old files
-rm -rf simv* csrc DVEfiles AN.DB
-
-# compile all of the files
-# Note that -sverilog is not strictly required- You can
-# remove the -sverilog if you change the type of the
-# localparam for the periods in the testbench file to
-# [63:0] from time
- vlogan -sverilog \
- clkmgr_dcm_tb.v \
- ../../implement/results/routed.v
-
-
-# prepare the simulation
-vcs -sdf max:clkmgr_dcm_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
- +libext+.v -debug clkmgr_dcm_tb.v ../../implement/results/routed.v
-
-# run the simulation
-./simv -ucli -i ucli_commands.key
-
-# launch the viewer
-#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key deleted file mode 100644 index b32669e..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ -
-call {$vcdpluson}
-run 50000ns
-call {$vcdplusclose}
-quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl deleted file mode 100644 index 6cc6e24..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl +++ /dev/null @@ -1 +0,0 @@ -gui_open_window Wave
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do deleted file mode 100644 index 7cc804b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do +++ /dev/null @@ -1,71 +0,0 @@ -# file: wave.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /clkmgr_dcm_tb/CLK_IN1
-add wave -noupdate /clkmgr_dcm_tb/COUNT
-add wave -noupdate /clkmgr_dcm_tb/RESET
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
-configure wave -namecolwidth 238
-configure wave -valuecolwidth 107
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ps
-update
-WaveRestoreZoom {0 ps} {74848022 ps}
|