aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--eim/build/Makefile20
-rw-r--r--eim/iseconfig/novena_eim.xise136
-rw-r--r--i2c/iseconfig/novena_i2c.xise129
3 files changed, 220 insertions, 65 deletions
diff --git a/eim/build/Makefile b/eim/build/Makefile
index 70f9f84..aab8470 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -16,6 +16,8 @@ vfiles = \
../../../common/core_selector/src/rtl/global_selector.v \
../../../common/core_selector/src/rtl/hash_selector.v \
../../../common/core_selector/src/rtl/rng_selector.v \
+ ../../../common/core_selector/src/rtl/cipher_selector.v \
+ ../../../common/core_selector/src/rtl/math_selector.v \
../../../../comm/eim/src/rtl/cdc_bus_pulse.v \
../../../../comm/eim/src/rtl/eim_arbiter_cdc.v \
../../../../comm/eim/src/rtl/eim_arbiter.v \
@@ -44,7 +46,23 @@ vfiles = \
../../../../rng/trng/src/rtl/trng_csprng.v \
../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
../../../../rng/trng/src/rtl/trng_mixer.v \
+ ../../../../cipher/aes/src/rtl/aes.v \
+ ../../../../cipher/aes/src/rtl/aes_core.v \
+ ../../../../cipher/aes/src/rtl/aes_decipher_block.v \
+ ../../../../cipher/aes/src/rtl/aes_encipher_block.v \
+ ../../../../cipher/aes/src/rtl/aes_inv_sbox.v \
+ ../../../../cipher/aes/src/rtl/aes_key_mem.v \
+ ../../../../cipher/aes/src/rtl/aes_sbox.v \
+ ../../../../cipher/chacha/src/rtl/chacha.v \
../../../../cipher/chacha/src/rtl/chacha_core.v \
- ../../../../cipher/chacha/src/rtl/chacha_qr.v
+ ../../../../cipher/chacha/src/rtl/chacha_qr.v \
+ ../../../../math/modexp/src/rtl/adder32.v \
+ ../../../../math/modexp/src/rtl/blockmem1r1w.v \
+ ../../../../math/modexp/src/rtl/blockmem2r1w.v \
+ ../../../../math/modexp/src/rtl/modexp.v \
+ ../../../../math/modexp/src/rtl/montprod.v \
+ ../../../../math/modexp/src/rtl/residue.v \
+ ../../../../math/modexp/src/rtl/shl32.v \
+ ../../../../math/modexp/src/rtl/shr32.v
include xilinx.mk
diff --git a/eim/iseconfig/novena_eim.xise b/eim/iseconfig/novena_eim.xise
index b29633e..b7708eb 100644
--- a/eim/iseconfig/novena_eim.xise
+++ b/eim/iseconfig/novena_eim.xise
@@ -17,95 +17,95 @@
<files>
<file xil_pn:name="../rtl/novena_eim.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../common/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../common/rtl/novena_clkmgr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/global_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../../../comm/eim/src/rtl/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../../../comm/eim/src/rtl/eim_da_phy.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../../../comm/eim/src/rtl/eim_indicator.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../../../comm/eim/src/rtl/eim.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
@@ -121,46 +121,46 @@
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../ucf/novena_eim.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../comm/eim/src/rtl/eim_regs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng_mixer.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng_fifo.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
@@ -168,12 +168,80 @@
</file>
<file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_qr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
+ <file xil_pn:name="../../../common/core_selector/src/rtl/math_selector.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_decipher_block.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_encipher_block.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_inv_sbox.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_key_mem.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_sbox.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/adder32.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem1r1w.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem2r1w.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/modexp.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/montprod.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/residue.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/shl32.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/shr32.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ </file>
<file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
diff --git a/i2c/iseconfig/novena_i2c.xise b/i2c/iseconfig/novena_i2c.xise
index fe2f4e1..d7e0224 100644
--- a/i2c/iseconfig/novena_i2c.xise
+++ b/i2c/iseconfig/novena_i2c.xise
@@ -17,82 +17,82 @@
<files>
<file xil_pn:name="../rtl/novena_i2c.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../common/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../common/rtl/novena_clkmgr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../ucf/novena_i2c.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/global_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../../../comm/coretest/src/rtl/coretest.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../../../comm/i2c/src/rtl/i2c_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
@@ -108,43 +108,43 @@
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../../../comm/i2c/src/rtl/i2c_regs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng_fifo.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../../rng/trng/src/rtl/trng_mixer.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
@@ -152,12 +152,80 @@
</file>
<file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_qr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_decipher_block.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_encipher_block.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_inv_sbox.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_key_mem.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_sbox.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/aes/src/rtl/aes.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/adder32.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem1r1w.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem2r1w.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/modexp.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/montprod.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/residue.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/shl32.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+ <file xil_pn:name="../../../../math/modexp/src/rtl/shr32.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ </file>
+ <file xil_pn:name="../../../common/core_selector/src/rtl/math_selector.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+ </file>
</files>
<properties>
@@ -455,6 +523,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 02:21:44 +0000