diff options
| -rw-r--r-- | config/config.cfg | 125 | ||||
| -rwxr-xr-x | config/config.py | 525 | ||||
| -rw-r--r-- | config/core_selector.v | 278 | ||||
| -rw-r--r-- | config/core_vfiles.mk | 42 | ||||
| -rw-r--r-- | eim/build/.gitignore | 2 | ||||
| -rw-r--r-- | eim/build/Makefile | 48 | ||||
| -rw-r--r-- | fmc/build/.gitignore | 2 | ||||
| -rw-r--r-- | fmc/build/Makefile | 47 | ||||
| -rw-r--r-- | i2c/build/.gitignore | 2 | ||||
| -rw-r--r-- | i2c/build/Makefile | 47 |
10 files changed, 130 insertions, 988 deletions
diff --git a/config/config.cfg b/config/config.cfg deleted file mode 100644 index f42813e..0000000 --- a/config/config.cfg +++ /dev/null @@ -1,125 +0,0 @@ -# Config file for the Cryptech Novena FPGA framework. -# -# Variables used in this file: -# -# default-section: Name of the configuration to build if the user -# doesn't specify one. Only meaningful in the default section. -# -# cores: A list of cores to build. Use with the --section option. -# -# vfiles: A list of Verilog files to include in the vfiles list when -# including a particular core. All (optional) cores must have a -# vfiles option, so that the configuration program knows what to put -# into core_vfiles.mk. -# -# requires: A list of other cores whose vfiles must be loaded to build -# this core. This has no effect on the generated core_selector.v -# file, and has no effect at all if an instance of a core named here -# is already included in the build. -# -# error_wire: boolean indicating whether the core wants a error wire. -# -# block_memory: boolean indicating whether the core uses block memory. -# Effect of this is a bit strange: setting it triggers generation of -# a one-cycle timing delay for every core in this build that does -# *not* use block memory. When no cores in the build use block -# memory, the delay isn't necessary and is therefore omitted. - -[default] -default-section = rsa - -[hash-only] -cores = sha1 sha256 sha512 - -[trng-only] -cores = trng - -[modexp-only] -cores = modexp - -[rsa] -cores = sha256 aes trng modexps6 - -[multi-test] -cores = sha256 aes aes chacha aes - -[sha1] -vfiles = - hash/sha1/src/rtl/sha1.v - hash/sha1/src/rtl/sha1_core.v - hash/sha1/src/rtl/sha1_w_mem.v - -[sha256] -vfiles = - hash/sha256/src/rtl/sha256.v - hash/sha256/src/rtl/sha256_core.v - hash/sha256/src/rtl/sha256_k_constants.v - hash/sha256/src/rtl/sha256_w_mem.v - -[sha512] -vfiles = - hash/sha512/src/rtl/sha512.v - hash/sha512/src/rtl/sha512_core.v - hash/sha512/src/rtl/sha512_h_constants.v - hash/sha512/src/rtl/sha512_k_constants.v - hash/sha512/src/rtl/sha512_w_mem.v - -[trng] -requires = chacha sha512 -vfiles = - rng/avalanche_entropy/src/rtl/avalanche_entropy.v - rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v - rng/rosc_entropy/src/rtl/rosc.v - rng/rosc_entropy/src/rtl/rosc_entropy.v - rng/rosc_entropy/src/rtl/rosc_entropy_core.v - rng/trng/src/rtl/trng.v - rng/trng/src/rtl/trng_csprng.v - rng/trng/src/rtl/trng_csprng_fifo.v - rng/trng/src/rtl/trng_mixer.v - -[aes] -vfiles = - cipher/aes/src/rtl/aes.v - cipher/aes/src/rtl/aes_core.v - cipher/aes/src/rtl/aes_decipher_block.v - cipher/aes/src/rtl/aes_encipher_block.v - cipher/aes/src/rtl/aes_inv_sbox.v - cipher/aes/src/rtl/aes_key_mem.v - cipher/aes/src/rtl/aes_sbox.v - -[chacha] -vfiles = - cipher/chacha/src/rtl/chacha.v - cipher/chacha/src/rtl/chacha_core.v - cipher/chacha/src/rtl/chacha_qr.v - -[modexps6] -block_memory = yes -error_wire = no -vfiles = - math/modexps6/src/rtl/modexps6_adder64_carry32.v - math/modexps6/src/rtl/modexps6_buffer_core.v - math/modexps6/src/rtl/modexps6_buffer_user.v - math/modexps6/src/rtl/modexps6_modinv32.v - math/modexps6/src/rtl/modexps6_montgomery_coeff.v - math/modexps6/src/rtl/modexps6_montgomery_multiplier.v - math/modexps6/src/rtl/modexps6_top.v - math/modexps6/src/rtl/modexps6_wrapper.v - math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v - math/modexps6/src/rtl/ipcore/multiplier_s6.v - math/modexps6/src/rtl/ipcore/subtractor_s6.v - -[modexp] -error_wire = no -vfiles = - math/modexp/src/rtl/adder.v - math/modexp/src/rtl/blockmem1r1w.v - math/modexp/src/rtl/blockmem2r1wptr.v - math/modexp/src/rtl/blockmem2r1w.v - math/modexp/src/rtl/blockmem2rptr1w.v - math/modexp/src/rtl/modexp.v - math/modexp/src/rtl/modexp_core.v - math/modexp/src/rtl/montprod.v - math/modexp/src/rtl/residue.v - math/modexp/src/rtl/shl.v - math/modexp/src/rtl/shr.v diff --git a/config/config.py b/config/config.py deleted file mode 100755 index de28e7b..0000000 --- a/config/config.py +++ /dev/null @@ -1,525 +0,0 @@ -#!/usr/bin/env python - -""" -Generate core_selector.v and core_vfiles.mk for a set of cores. -""" - -# History of Cryptech bus addressing scheme, as best I understand it. -# -# The old old addressing scheme that Joachim and Paul came up with -# was: -# -# 3 bits of segment selector [16:14] -# 6 bits of core selector [13:8] -# 8 bits of register selector [7:0] -# -# modexp6s needed more register bits than that, so Pavel changed -# addressing within the math segment to: -# -# 3 bits of segment selector [16:14] -# 4 bits of core selector [13:10] -# 10 bits of register selector [9:0] -# -# Meanwhile, Paul eliminated segments entirely when writing the -# ancestor of this script, resulting in: -# -# 9 bits of core selector [16:8] -# 8 bits of register selector [7:0] -# -# Taking Pavel's and Paul's changes together, we'd get: -# -# 7 bits of core selector [16:10] -# 10 bits of register selector [9:0] -# -# Except that this would waste space for most cores, and make things -# very confusing for the TRNG cores. So, instead, we keep Paul's -# two-level (no segment) scheme and handle modexps6 as a set of four -# contiguous "cores" with a 10-bit composite register selector. - -# The modexps6 core drags in a one clock cycle delay to other cores, -# to compensate for the extra clock cycle consumed by the block -# memories used in the modexps6 core. We probably want a general -# solution for this, because we're going to run into this problem for -# any core that handles arguments big enough to require block memory. - -# To Do: -# -# - Consider automating the one-clock-cycle delay stuff by adding -# another boolean flag to the config file. Default would be no -# delay, if any included core sets the "I use block memories" flag, -# all other cores would get the delay. Slightly tedious but -# something we can calculate easily enough, and probably an -# improvement over wiring in the delay when nothing needs it. -# -# - Rename script and its config file to something more meaningful. -# -# - Figure out whether this really belongs in the novena repository at -# all, seems more generic than that. - - -def main(): - """ - Parse arguments and config file, generate core list, generate output. - """ - - from argparse import ArgumentParser, FileType, ArgumentDefaultsHelpFormatter - from sys import exit - - parser = ArgumentParser(description = __doc__, formatter_class = ArgumentDefaultsHelpFormatter) - parser.add_argument("-d", "--debug", help = "enable debugging", action = "store_true") - parser.add_argument("-s", "--section", help = "config file section") - parser.add_argument("-c", "--config", help = "configuration file", default = "config.cfg", type = FileType("r")) - parser.add_argument("--verilog", help = "verilog output file", default = "core_selector.v", type = FileType("w")) - parser.add_argument("--makefile", help = "output makefile", default = "core_vfiles.mk", type = FileType("w")) - parser.add_argument("core", help = "name(s) of core(s)", nargs = "*") - args = parser.parse_args() - - try: - cfg = RawConfigParser() - cfg.readfp(args.config) - - if args.core: - cores = args.core - else: - section = args.section or cfg.get("default", "default-section") - cores = cfg.get(section, "cores").split() - - cores.insert(0, "board_regs") - cores.insert(1, "comm_regs") - - cores = tuple(Core.new(core) for core in cores) - - core_number = 0 - for core in cores: - core_number = core.assign_core_number(core_number) - - for core in cores: - core.configure(cfg) - - if False: - - # For some reason, attempting to optimize out the delay - # code entirely results in a non-working bitstream. Don't - # know why, disabling the optimization works, so just do - # that for now. - - Core.need_one_cycle_delay = any(core.block_memory for core in cores) - - args.verilog.write(createModule_template.format( - addrs = "".join(core.createAddr() for core in cores), - insts = "".join(core.createInstance() for core in cores), - muxes = "".join(core.createMux() for core in cores))) - - args.makefile.write(listVfiles_template.format( - vfiles = "".join(core.listVfiles() for core in cores))) - - except Exception, e: - if args.debug: - raise - exit(str(e)) - - -try: - import ConfigParser as configparser -except ImportError: - import configparser - -class RawConfigParser(configparser.RawConfigParser): - """ - RawConfigParser with a few extensions. - """ - - def getboolean(self, section, option, default = False): - if self.has_option(section, option): - # RawConfigParser is an old-stle class, super() doesn't work, feh. - return configparser.RawConfigParser.getboolean(self, section, option) - else: - return default - - def getvalues(self, section, option): - if self.has_option(section, option): - for value in self.get(section, option).split(): - yield value - - -class Core(object): - """ - Data and methods for a generic core. We can use this directly for - most cores, a few are weird and require subclassing to override - particular methods. - """ - - # Class variable tracking how many times a particular core has - # been instantiated. This controls instance numbering. - - _instance_count = {} - - # Class variable mapping core name to subclass for special cases. - - special_class = {} - - # Class variable recording whether we need a one-cycle delay to - # compensate for block memories. - - need_one_cycle_delay = True - - def __init__(self, name): - self.name = name - self.core_number = None - self.vfiles = [] - self.error_wire = True - self.block_memory = False - self.instance_number = self._instance_count.get(name, 0) - self._instance_count[name] = self.instance_number + 1 - - @classmethod - def new(cls, name): - return cls.special_class.get(name, cls)(name) - - def assign_core_number(self, n): - self.core_number = n - return n + 1 - - def configure(self, cfg): - if self.instance_number == 0: - self.vfiles.extend(cfg.getvalues(self.name, "vfiles")) - for required in cfg.getvalues(self.name, "requires"): - if required not in self._instance_count: - self.vfiles.extend(cfg.getvalues(required, "vfiles")) - self.error_wire = cfg.getboolean(self.name, "error_wire", self.error_wire) - self.block_memory = cfg.getboolean(self.name, "block_memory", self.block_memory) - - @property - def instance_name(self): - if self._instance_count[self.name] > 1: - return "{}_{}".format(self.name, self.instance_number) - else: - return self.name - - @property - def upper_instance_name(self): - return self.instance_name.upper() - - @property - def reset_pin(self): - return ".reset_n(sys_rst_n)" - - @property - def error_port(self): - return ",\n .error(error_{core.instance_name})".format(core = self) if self.error_wire else "" - - @property - def one_cycle_delay(self): - return one_cycle_delay_template.format(core = self) if self.need_one_cycle_delay and not self.block_memory else "" - - @property - def mux_data_reg(self): - return "read_data_" + self.instance_name + ("_reg" if self.need_one_cycle_delay and not self.block_memory else "") - - @property - def mux_error_reg(self): - return "error_" + self.instance_name if self.error_wire else "0" - - def createInstance(self): - return createInstance_template_generic.format(core = self) - - def createAddr(self): - return createAddr_template.format(core = self) - - def createMux(self): - return createMux_template.format(core = self, core0 = self) - - def listVfiles(self): - return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles) - - -class SubCore(Core): - """" - Override mux handling for TRNG's sub-cores. - """ - - def __init__(self, name, parent): - super(SubCore, self).__init__(name) - self.parent = parent - - def createMux(self): - return createMux_template.format(core = self, core0 = self.parent) - - -class TRNGCore(Core): - """ - The TRNG core has an internal mux with slots for 15 sub-cores, - most of which are empty. This is a bit of a mess. - - Mostly this means that our method calls have to iterate over all - of the subcores after handling the base TRNG core, but we also use - different templates, and fiddle with addresses a bit. - - Mux numbers have to be dug out of the TRNG Verilog source. - """ - - # TRNG subcore name -> internal mux number. - subcore_parameters = dict(avalanche_entropy = 0x1, - rosc_entropy = 0x2, - trng_mixer = 0x3, - trng_csprng = 0x4) - - def __init__(self, name): - super(TRNGCore, self).__init__(name) - self.subcores = tuple(SubCore(name, self) - for name in sorted(self.subcore_parameters, - key = lambda x: self.subcore_parameters[x])) - - def assign_core_number(self, n): - n = super(TRNGCore, self).assign_core_number(n) - for subcore in self.subcores: - subcore.assign_core_number(self.core_number + self.subcore_parameters[subcore.name]) - return n + 15 - - @property - def last_subcore_upper_instance_name(self): - return self.subcores[-1].upper_instance_name - - def createInstance(self): - return createInstance_template_TRNG.format(core = self) - - def createAddr(self): - return super(TRNGCore, self).createAddr() + "".join(subcore.createAddr() for subcore in self.subcores) - - def createMux(self): - return super(TRNGCore, self).createMux() + "".join(subcore.createMux() for subcore in self.subcores) - - -class ModExpS6Core(Core): - """ - ModExpS6 core consumes as much space as four ordinary cores, and - uses different templates to handle the differences in timing and - addressing. - """ - - def assign_core_number(self, n): - n = super(ModExpS6Core, self).assign_core_number(n) - return n + 3 - - def createInstance(self): - return createInstance_template_ModExpS6.format(core = self) - - def createMux(self): - return createMux_modexps6_template.format(core = self, core0 = self) - - -# Hook special classes in as handlers for the cores that require them. - -Core.special_class.update( - trng = TRNGCore, - modexps6 = ModExpS6Core) - - -# Templates (format strings), here instead of inline in the functions -# that use them, both because some of these are shared between -# multiple functions and because it's easier to read these (and get -# the indentation right) when the're separate. - -# Template used by .createAddr() methods. - -createAddr_template = """\ - localparam CORE_ADDR_{core.upper_instance_name:21s} = 9'h{core.core_number:02x}; -""" - -# Template used by Core.createInstance(). - -createInstance_template_generic = """\ - //---------------------------------------------------------------- - // {core.upper_instance_name} - //---------------------------------------------------------------- - wire enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name}); - wire [31: 0] read_data_{core.instance_name}; - wire error_{core.instance_name}; - - {core.name} {core.instance_name}_inst - ( - .clk(sys_clk), - {core.reset_pin}, - - .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_{core.instance_name}){core.error_port} - ); - -{core.one_cycle_delay} - -""" - -# Template used by ModExpS6Core.createInstance(). This is different -# enough from the base template that it's easier to make this separate. - -createInstance_template_ModExpS6 = """\ - //---------------------------------------------------------------- - // {core.upper_instance_name} - //---------------------------------------------------------------- - wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 9'h03); - wire [31: 0] read_data_{core.instance_name}; - wire [1:0] {core.instance_name}_prefix = addr_core_num[1:0] - CORE_ADDR_{core.upper_instance_name}; - - {core.name}_wrapper {core.instance_name}_inst - ( - .clk(sys_clk), - {core.reset_pin}, - - .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address({{{core.instance_name}_prefix, addr_core_reg}}), - .write_data(sys_write_data), - .read_data(read_data_{core.instance_name}) - ); - - -""" - -# Template used by TRNGCore.createInstance(); this is different enough -# from the generic template that it's (probably) clearer to have this -# separate. - -createInstance_template_TRNG = """\ - //---------------------------------------------------------------- - // {core.upper_instance_name} - //---------------------------------------------------------------- - wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 9'h0f); - wire [31: 0] read_data_{core.instance_name}; - wire error_{core.instance_name}; - wire [3:0] {core.instance_name}_prefix = addr_core_num[3:0] - CORE_ADDR_{core.upper_instance_name}; - - {core.name} {core.instance_name}_inst - ( - .clk(sys_clk), - {core.reset_pin}, - - .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address({{{core.instance_name}_prefix, addr_core_reg}}), - .write_data(sys_write_data), - .read_data(read_data_{core.instance_name}), - .error(error_{core.instance_name}), - - .avalanche_noise(noise), - .debug(debug) - ); - -{core.one_cycle_delay} - -""" - -# Template for one-cycle delay code. - -one_cycle_delay_template = """\ - reg [31: 0] read_data_{core.instance_name}_reg; - always @(posedge sys_clk) - read_data_{core.instance_name}_reg <= read_data_{core.instance_name}; -""" - -# Template for .createMux() methods. - -createMux_template = """\ - CORE_ADDR_{core.upper_instance_name}: - begin - sys_read_data_mux = {core0.mux_data_reg}; - sys_error_mux = {core0.mux_error_reg}; - end -""" - -# Template for ModExpS6.createMux() method. - -createMux_modexps6_template = """\ - CORE_ADDR_{core.upper_instance_name} + 0, - CORE_ADDR_{core.upper_instance_name} + 1, - CORE_ADDR_{core.upper_instance_name} + 2, - CORE_ADDR_{core.upper_instance_name} + 3: - begin - sys_read_data_mux = {core0.mux_data_reg}; - sys_error_mux = {core0.mux_error_reg}; - end -""" - - -# Top-level (createModule) template. - -createModule_template = """\ -// NOTE: This file is generated; do not edit by hand. - -module core_selector - ( - input wire sys_clk, - input wire sys_rst_n, - - input wire [16: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31: 0] sys_read_data, - input wire [31: 0] sys_write_data, - output wire sys_error, - - input wire noise, - output wire [7 : 0] debug - ); - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 9 bits specify core being addressed - wire [ 8: 0] addr_core_num = sys_eim_addr[16: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- -{addrs} - -{insts} - //---------------------------------------------------------------- - // Output (Read Data) Multiplexer - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - - case (addr_core_num) -{muxes} - default: - begin - sys_read_data_mux = {{32{{1'b0}}}}; - sys_error_mux = 1; - end - endcase - - -endmodule - - -//====================================================================== -// EOF core_selector.v -//====================================================================== -""" - -# Template for makefile snippet listing Verilog source files. - -listVfiles_template = """\ -# NOTE: This file is generated; do not edit by hand. - -vfiles +={vfiles} -""" - -# Run main program. - -if __name__ == "__main__": - main() diff --git a/config/core_selector.v b/config/core_selector.v deleted file mode 100644 index 298c39e..0000000 --- a/config/core_selector.v +++ /dev/null @@ -1,278 +0,0 @@ -// NOTE: This file is generated; do not edit by hand. - -module core_selector - ( - input wire sys_clk, - input wire sys_rst_n, - - input wire [16: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31: 0] sys_read_data, - input wire [31: 0] sys_write_data, - output wire sys_error, - - input wire noise, - output wire [7 : 0] debug - ); - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 9 bits specify core being addressed - wire [ 8: 0] addr_core_num = sys_eim_addr[16: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_BOARD_REGS = 9'h00; - localparam CORE_ADDR_COMM_REGS = 9'h01; - localparam CORE_ADDR_SHA256 = 9'h02; - localparam CORE_ADDR_AES = 9'h03; - localparam CORE_ADDR_TRNG = 9'h04; - localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h05; - localparam CORE_ADDR_ROSC_ENTROPY = 9'h06; - localparam CORE_ADDR_TRNG_MIXER = 9'h07; - localparam CORE_ADDR_TRNG_CSPRNG = 9'h08; - localparam CORE_ADDR_MODEXPS6 = 9'h14; - - - //---------------------------------------------------------------- - // BOARD_REGS - //---------------------------------------------------------------- - wire enable_board_regs = (addr_core_num == CORE_ADDR_BOARD_REGS); - wire [31: 0] read_data_board_regs; - wire error_board_regs; - - board_regs board_regs_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_board_regs & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_board_regs), - .error(error_board_regs) - ); - - reg [31: 0] read_data_board_regs_reg; - always @(posedge sys_clk) - read_data_board_regs_reg <= read_data_board_regs; - - - //---------------------------------------------------------------- - // COMM_REGS - //---------------------------------------------------------------- - wire enable_comm_regs = (addr_core_num == CORE_ADDR_COMM_REGS); - wire [31: 0] read_data_comm_regs; - wire error_comm_regs; - - comm_regs comm_regs_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_comm_regs & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_comm_regs), - .error(error_comm_regs) - ); - - reg [31: 0] read_data_comm_regs_reg; - always @(posedge sys_clk) - read_data_comm_regs_reg <= read_data_comm_regs; - - - //---------------------------------------------------------------- - // SHA256 - //---------------------------------------------------------------- - wire enable_sha256 = (addr_core_num == CORE_ADDR_SHA256); - wire [31: 0] read_data_sha256; - wire error_sha256; - - sha256 sha256_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha256), - .error(error_sha256) - ); - - reg [31: 0] read_data_sha256_reg; - always @(posedge sys_clk) - read_data_sha256_reg <= read_data_sha256; - - - //---------------------------------------------------------------- - // AES - //---------------------------------------------------------------- - wire enable_aes = (addr_core_num == CORE_ADDR_AES); - wire [31: 0] read_data_aes; - wire error_aes; - - aes aes_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_aes & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_aes), - .error(error_aes) - ); - - reg [31: 0] read_data_aes_reg; - always @(posedge sys_clk) - read_data_aes_reg <= read_data_aes; - - - //---------------------------------------------------------------- - // TRNG - //---------------------------------------------------------------- - wire enable_trng = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG + 9'h0f); - wire [31: 0] read_data_trng; - wire error_trng; - wire [3:0] trng_prefix = addr_core_num[3:0] - CORE_ADDR_TRNG; - - trng trng_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_trng & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address({trng_prefix, addr_core_reg}), - .write_data(sys_write_data), - .read_data(read_data_trng), - .error(error_trng), - - .avalanche_noise(noise), - .debug(debug) - ); - - reg [31: 0] read_data_trng_reg; - always @(posedge sys_clk) - read_data_trng_reg <= read_data_trng; - - - //---------------------------------------------------------------- - // MODEXPS6 - //---------------------------------------------------------------- - wire enable_modexps6 = (addr_core_num >= CORE_ADDR_MODEXPS6) && (addr_core_num <= CORE_ADDR_MODEXPS6 + 9'h03); - wire [31: 0] read_data_modexps6; - wire [1:0] modexps6_prefix = addr_core_num[1:0] - CORE_ADDR_MODEXPS6; - - modexps6_wrapper modexps6_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_modexps6 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address({modexps6_prefix, addr_core_reg}), - .write_data(sys_write_data), - .read_data(read_data_modexps6) - ); - - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexer - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - - case (addr_core_num) - CORE_ADDR_BOARD_REGS: - begin - sys_read_data_mux = read_data_board_regs_reg; - sys_error_mux = error_board_regs; - end - CORE_ADDR_COMM_REGS: - begin - sys_read_data_mux = read_data_comm_regs_reg; - sys_error_mux = error_comm_regs; - end - CORE_ADDR_SHA256: - begin - sys_read_data_mux = read_data_sha256_reg; - sys_error_mux = error_sha256; - end - CORE_ADDR_AES: - begin - sys_read_data_mux = read_data_aes_reg; - sys_error_mux = error_aes; - end - CORE_ADDR_TRNG: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_AVALANCHE_ENTROPY: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_ROSC_ENTROPY: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_TRNG_MIXER: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_TRNG_CSPRNG: - begin - sys_read_data_mux = read_data_trng_reg; - sys_error_mux = error_trng; - end - CORE_ADDR_MODEXPS6 + 0, - CORE_ADDR_MODEXPS6 + 1, - CORE_ADDR_MODEXPS6 + 2, - CORE_ADDR_MODEXPS6 + 3: - begin - sys_read_data_mux = read_data_modexps6; - sys_error_mux = 0; - end - - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - endcase - - -endmodule - - -//====================================================================== -// EOF core_selector.v -//====================================================================== diff --git a/config/core_vfiles.mk b/config/core_vfiles.mk deleted file mode 100644 index 4020234..0000000 --- a/config/core_vfiles.mk +++ /dev/null @@ -1,42 +0,0 @@ -# NOTE: This file is generated; do not edit by hand. - -vfiles += \ - $(CORE_TREE)/hash/sha256/src/rtl/sha256.v \ - $(CORE_TREE)/hash/sha256/src/rtl/sha256_core.v \ - $(CORE_TREE)/hash/sha256/src/rtl/sha256_k_constants.v \ - $(CORE_TREE)/hash/sha256/src/rtl/sha256_w_mem.v \ - $(CORE_TREE)/cipher/aes/src/rtl/aes.v \ - $(CORE_TREE)/cipher/aes/src/rtl/aes_core.v \ - $(CORE_TREE)/cipher/aes/src/rtl/aes_decipher_block.v \ - $(CORE_TREE)/cipher/aes/src/rtl/aes_encipher_block.v \ - $(CORE_TREE)/cipher/aes/src/rtl/aes_inv_sbox.v \ - $(CORE_TREE)/cipher/aes/src/rtl/aes_key_mem.v \ - $(CORE_TREE)/cipher/aes/src/rtl/aes_sbox.v \ - $(CORE_TREE)/rng/avalanche_entropy/src/rtl/avalanche_entropy.v \ - $(CORE_TREE)/rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \ - $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc.v \ - $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc_entropy.v \ - $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc_entropy_core.v \ - $(CORE_TREE)/rng/trng/src/rtl/trng.v \ - $(CORE_TREE)/rng/trng/src/rtl/trng_csprng.v \ - $(CORE_TREE)/rng/trng/src/rtl/trng_csprng_fifo.v \ - $(CORE_TREE)/rng/trng/src/rtl/trng_mixer.v \ - $(CORE_TREE)/cipher/chacha/src/rtl/chacha.v \ - $(CORE_TREE)/cipher/chacha/src/rtl/chacha_core.v \ - $(CORE_TREE)/cipher/chacha/src/rtl/chacha_qr.v \ - $(CORE_TREE)/hash/sha512/src/rtl/sha512.v \ - $(CORE_TREE)/hash/sha512/src/rtl/sha512_core.v \ - $(CORE_TREE)/hash/sha512/src/rtl/sha512_h_constants.v \ - $(CORE_TREE)/hash/sha512/src/rtl/sha512_k_constants.v \ - $(CORE_TREE)/hash/sha512/src/rtl/sha512_w_mem.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_adder64_carry32.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_buffer_core.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_buffer_user.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_modinv32.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_montgomery_coeff.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_montgomery_multiplier.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_top.v \ - $(CORE_TREE)/math/modexps6/src/rtl/modexps6_wrapper.v \ - $(CORE_TREE)/math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v \ - $(CORE_TREE)/math/modexps6/src/rtl/ipcore/multiplier_s6.v \ - $(CORE_TREE)/math/modexps6/src/rtl/ipcore/subtractor_s6.v diff --git a/eim/build/.gitignore b/eim/build/.gitignore index 01d7e9c..2eb6775 100644 --- a/eim/build/.gitignore +++ b/eim/build/.gitignore @@ -50,3 +50,5 @@ usage_statistics_webtalk.html webtalk.log xlnx_auto* xst +core_selector.v +core_vfiles.mk diff --git a/eim/build/Makefile b/eim/build/Makefile index a7eec60..bd9e8b8 100644 --- a/eim/build/Makefile +++ b/eim/build/Makefile @@ -9,14 +9,41 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) # Parameters to xilinx.mk. -project = novena_eim +project ?= novena_eim vendor = xilinx family = spartan6 part = xc6slx45csg324-3 top_module = novena_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -ucf = ../ucf/$(project).ucf +ucf ?= ../ucf/$(project).ucf +#ucf ?= ../ucf/$(project)-dev_bridge_board.ucf + +all: $(project).bit + +# Build the default core_selector if it doesn't already exist. + +CONFIG = $(CORE_TREE)/platform/common/config +core_selector.v core_vfiles.mk: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg + +# Build some different configurations + +bare: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare + $(MAKE) project=$(project)_bare ucf=$(ucf) + +trng: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng + $(MAKE) project=$(project)_trng ucf=$(ucf) + +hash: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash + $(MAKE) project=$(project)_hash ucf=$(ucf) + +rsa: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa + $(MAKE) project=$(project)_rsa ucf=$(ucf) # Verilog files that always go with builds on this platform. @@ -25,7 +52,7 @@ vfiles = \ $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \ $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \ $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \ - $(CORE_TREE)/platform/novena/config/core_selector.v \ + ./core_selector.v \ $(CORE_TREE)/comm/eim/src/rtl/cdc_bus_pulse.v \ $(CORE_TREE)/comm/eim/src/rtl/eim_arbiter_cdc.v \ $(CORE_TREE)/comm/eim/src/rtl/eim_arbiter.v \ @@ -36,13 +63,22 @@ vfiles = \ # Verilog files selected by the core configuration script. --include $(CORE_TREE)/platform/novena/config/core_vfiles.mk +-include ./core_vfiles.mk include xilinx.mk -# Fun extras for running verlator as a linter. +# 'clean' target collects files by project name, and we just broke that + +junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \ + *.ngd *.ngm *.pcf *.post_map.twr *.post_map.twx *.prj *.prm *.psr \ + *.scr *.srp *.twr *.twx *_bd.bmm *_bitgen.xwb *_bitgen.xwbt \ + *_err.twr *_err.twx *_par.grf *_par.ncd *_par.pad *_par.par \ + *_par.ptwx *_par.unroutes *_par.xpi *_par_pad.csv *_par_pad.txt \ + *_summary.xml *_usage.xml + +# Fun extras for running verilator as a linter. -VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME +VERILATOR_FLAGS = --lint-only --top-module $(top_module) -Wall -Wno-fatal -Wno-DECLFILENAME lint: verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v diff --git a/fmc/build/.gitignore b/fmc/build/.gitignore index 865bda8..66d2673 100644 --- a/fmc/build/.gitignore +++ b/fmc/build/.gitignore @@ -51,3 +51,5 @@ par_usage_statistics.html webtalk.log _xmsgs default.xreport +core_selector.v +core_vfiles.mk diff --git a/fmc/build/Makefile b/fmc/build/Makefile index 1b81656..a7e8755 100644 --- a/fmc/build/Makefile +++ b/fmc/build/Makefile @@ -9,14 +9,40 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) # Parameters to xilinx.mk. -project = novena_fmc +project ?= novena_fmc vendor = xilinx family = spartan6 part = xc6slx45csg324-3 top_module = novena_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -ucf = ../ucf/$(project).ucf +ucf ?= ../ucf/$(project).ucf + +all: $(project).bit + +# Build the default core_selector if it doesn't already exist. + +CONFIG = $(CORE_TREE)/platform/common/config +core_selector.v core_vfiles.mk: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg + +# Build some different configurations + +bare: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare + $(MAKE) project=$(project)_bare ucf=$(ucf) + +trng: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng + $(MAKE) project=$(project)_trng ucf=$(ucf) + +hash: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash + $(MAKE) project=$(project)_hash ucf=$(ucf) + +rsa: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa + $(MAKE) project=$(project)_rsa ucf=$(ucf) # Verilog files that always go with builds on this platform. @@ -25,7 +51,7 @@ vfiles = \ $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \ $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \ $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \ - $(CORE_TREE)/platform/novena/config/core_selector.v \ + ./core_selector.v \ $(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \ @@ -35,13 +61,22 @@ vfiles = \ # Verilog files selected by the core configuration script. --include $(CORE_TREE)/platform/novena/config/core_vfiles.mk +-include ./core_vfiles.mk include xilinx.mk -# Fun extras for running verlator as a linter. +# 'clean' target collects files by project name, and we just broke that + +junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \ + *.ngd *.ngm *.pcf *.post_map.twr *.post_map.twx *.prj *.prm *.psr \ + *.scr *.srp *.twr *.twx *_bd.bmm *_bitgen.xwb *_bitgen.xwbt \ + *_err.twr *_err.twx *_par.grf *_par.ncd *_par.pad *_par.par \ + *_par.ptwx *_par.unroutes *_par.xpi *_par_pad.csv *_par_pad.txt \ + *_summary.xml *_usage.xml + +# Fun extras for running verilator as a linter. -VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME +VERILATOR_FLAGS = --lint-only --top-module $(top_module) -Wall -Wno-fatal -Wno-DECLFILENAME lint: verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v diff --git a/i2c/build/.gitignore b/i2c/build/.gitignore index 01d7e9c..2eb6775 100644 --- a/i2c/build/.gitignore +++ b/i2c/build/.gitignore @@ -50,3 +50,5 @@ usage_statistics_webtalk.html webtalk.log xlnx_auto* xst +core_selector.v +core_vfiles.mk diff --git a/i2c/build/Makefile b/i2c/build/Makefile index 441b67a..bc1bd14 100644 --- a/i2c/build/Makefile +++ b/i2c/build/Makefile @@ -9,14 +9,40 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) # Parameters to xilinx.mk. -project = novena_eim +project ?= novena_i2c vendor = xilinx family = spartan6 part = xc6slx45csg324-3 top_module = novena_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -ucf = ../ucf/$(project).ucf +ucf ?= ../ucf/$(project).ucf + +all: $(project).bit + +# Build the default core_selector if it doesn't already exist. + +CONFIG = $(CORE_TREE)/platform/common/config +core_selector.v core_vfiles.mk: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg + +# Build some different configurations + +bare: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare + $(MAKE) project=$(project)_bare ucf=$(ucf) + +trng: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng + $(MAKE) project=$(project)_trng ucf=$(ucf) + +hash: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash + $(MAKE) project=$(project)_hash ucf=$(ucf) + +rsa: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa + $(MAKE) project=$(project)_rsa ucf=$(ucf) # Verilog files that always go with builds on this platform. @@ -25,20 +51,29 @@ vfiles = \ $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \ $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \ $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \ - $(CORE_TREE)/platform/novena/config/core_selector.v \ + ./core_selector.v \ $(CORE_TREE)/comm/i2c/src/rtl/i2c_regs.v \ $(CORE_TREE)/comm/i2c/src/rtl/i2c_core.v \ $(CORE_TREE)/comm/coretest/src/rtl/coretest.v # Verilog files selected by the core configuration script. --include $(CORE_TREE)/platform/novena/config/core_vfiles.mk +-include ./core_vfiles.mk include xilinx.mk -# Fun extras for running verlator as a linter. +# 'clean' target collects files by project name, and we just broke that + +junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \ + *.ngd *.ngm *.pcf *.post_map.twr *.post_map.twx *.prj *.prm *.psr \ + *.scr *.srp *.twr *.twx *_bd.bmm *_bitgen.xwb *_bitgen.xwbt \ + *_err.twr *_err.twx *_par.grf *_par.ncd *_par.pad *_par.par \ + *_par.ptwx *_par.unroutes *_par.xpi *_par_pad.csv *_par_pad.txt \ + *_summary.xml *_usage.xml + +# Fun extras for running verilator as a linter. -VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME +VERILATOR_FLAGS = --lint-only --top-module $(top_module) -Wall -Wno-fatal -Wno-DECLFILENAME lint: verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v |