diff options
| -rwxr-xr-x | config/config.py | 46 |
1 files changed, 31 insertions, 15 deletions
diff --git a/config/config.py b/config/config.py index 814826f..0ec1274 100755 --- a/config/config.py +++ b/config/config.py @@ -25,26 +25,36 @@ Generate core_selector.v for a set of cores. # 9 bits of core selector [16:8] # 8 bits of register selector [7:0] # -# Taking Pavel's and Paul's changes together, we want: +# Taking Pavel's and Paul's changes together, we'd get: # # 7 bits of core selector [16:10] # 10 bits of register selector [9:0] # -# Open issue: what effect does all this have on the sub-core muxing -# within trng cores? trng core plus its (currently) four sub-cores -# still takes up more than one new core slot even if trng uses the old -# scheme internally. How many slots should we allocate, and what -# addressing scheme is the trng core expecting to see? -# -# So perhaps a better plan would be to keep Paul's scheme and just -# give modexps6 four core's worth of space, passing a 10 bit composite -# address constructed in much the same way as the trng template -# already does. +# Except that this would waste space for most cores, and make things +# very confusing for the TRNG cores. So, instead, we keep Paul's +# two-level (no segment) scheme and handle modexps6 as a set of four +# consecutive "cores" with a 10-bit composite register selector. + +# The modexps6 core also drags in a one clock cycle delay to other +# cores, to compensate for the extra clock cycle consumed by the block +# memories used in the modexps6 core. -# Unrelated: Timing delays. Paul added extra registers to slow cores -# other than modexps6 down by one clock cycle, to compensate for the -# one cycle delay that seems to be built into the block memories that -# modexps6 uses. Templates will need to reflect that somehow. +# To Do: +# +# - Move reset-high/reset-low to a boolean variable in the config +# file, simplify Core classes accordingly. +# +# - Consider automating the one-clock-cycle delay stuff by adding +# another boolean flag to the config file. Default would be no +# delay, if any included core sets the "I use block memories" flag, +# all other cores would get the delay. Slightly tedious but +# something we can calculate easily enough, and probably an +# improvement over wiring in the delay when nothing needs it. +# +# - Rename script and its config file to something more meaningful. +# +# - Figure out whether this really belongs in the novena repository at +# all, seems more generic than that. def main(): """ @@ -224,6 +234,11 @@ class TRNGCore(InvertedResetCore): class ModExpS6Core(Core): + """ + ModExpS6 core consumes as much space as four ordinary cores, and + uses different templates to handle the differences in timing and + addressing. + """ def assign_core_number(self, n): n = super(ModExpS6Core, self).assign_core_number(n) @@ -237,6 +252,7 @@ class ModExpS6Core(Core): # Hook special classes in as handlers for the cores that require them. +# Moving the reset-high/reset-low logic to the config file should simplify this. Core.special_class.update( trng = TRNGCore, |