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authorRob Austein <sra@hactrn.net>2015-09-26 13:21:01 -0400
committerRob Austein <sra@hactrn.net>2015-09-26 13:21:01 -0400
commit19e4044fcf47360dcc5aa68f6eae5a62a6cdb61b (patch)
treea73d95a6a02b3d9311abc7ffe6ad7d7fab42d17b /config
parentf43b493bcc7dfe1d6b49faad6dc32c8948573e29 (diff)
Sorted out reset pins (I think). Seems our various core authors have
different opinions about whether reset should be high or low, and the core selector code is responsible for making this right. Hmm. Address map may still be wrong, as addressing scheme seems to have changed while the core_select branch was gathering dust.
Diffstat (limited to 'config')
-rwxr-xr-xconfig/config.py69
-rw-r--r--config/core_selector.v4
-rw-r--r--config/core_vfiles.mk34
3 files changed, 60 insertions, 47 deletions
diff --git a/config/config.py b/config/config.py
index ddf7d0b..970b339 100755
--- a/config/config.py
+++ b/config/config.py
@@ -101,6 +101,10 @@ class Core(object):
def upper_instance_name(self):
return self.instance_name.upper()
+ @property
+ def reset_pin(self):
+ return ".rst(sys_rst)"
+
def createInstance(self):
return createInstance_template_generic.format(core = self)
@@ -114,14 +118,15 @@ class Core(object):
return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles)
-class BoardCore(Core):
+class InvertedResetCore(Core):
"""
- Board-level cores have a slightly different API, which we handle
- with a different template, at least for now.
+ Core which inverts the reset signal. Seems to vary by author.
+ No, I don't know why we don't just pick one convention or the other.
"""
- def createInstance(self):
- return createInstance_template_board.format(core = self)
+ @property
+ def reset_pin(self):
+ return ".reset_n(~sys_rst)"
class SubCore(Core):
@@ -137,7 +142,7 @@ class SubCore(Core):
return createMux_template.format(core = self, core0 = self.parent)
-class TRNGCore(Core):
+class TRNGCore(InvertedResetCore):
"""
The TRNG core has an internal mux and a collection of sub-cores.
Mostly this means that our method calls have to iterate over all
@@ -166,12 +171,16 @@ class TRNGCore(Core):
def createMux(self):
return super(TRNGCore, self).createMux() + "".join(subcore.createMux() for subcore in self.subcores)
-# Hook special classes in as handlers for the cores that require them
+# Hook special classes in as handlers for the cores that require them.
Core.special_class.update(
- board_regs = BoardCore,
- comm_regs = BoardCore,
- trng = TRNGCore)
+ trng = TRNGCore,
+ aes = InvertedResetCore,
+ chacha = InvertedResetCore,
+ sha1 = InvertedResetCore,
+ sha256 = InvertedResetCore,
+ sha512 = InvertedResetCore,
+ modexp = InvertedResetCore)
# Templates (format strings), here instead of inline in the functions
@@ -191,14 +200,14 @@ createInstance_template_generic = """\
//----------------------------------------------------------------
// {core.upper_instance_name}
//----------------------------------------------------------------
- wire enable_{core.instance_name} = sys_ena && (addr_core_num == CORE_ADDR_{core.upper_instance_name});
+ wire enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name});
wire [31: 0] read_data_{core.instance_name};
wire error_{core.instance_name};
{core.name} {core.instance_name}_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ {core.reset_pin},
.cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -211,41 +220,9 @@ createInstance_template_generic = """\
"""
-# Template used by BoardCore.createInstance(). This has minor
-# differences from the generic template, maybe we can merge them, or
-# maybe we can do something about the (gratuitous?) differences that
-# make this necessary.
-
-createInstance_template_board = """\
- //----------------------------------------------------------------
- // {core.upper_instance_name}
- //----------------------------------------------------------------
- wire enable_{core.instance_name} = sys_ena && (addr_core_num == CORE_ADDR_{core.upper_instance_name});
- wire [31: 0] read_data_{core.instance_name};
- wire error_{core.instance_name};
-
- {core.name} {core.instance_name}_inst
- (
- .clk(sys_clk),
- .rst(sys_rst),
-
- .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)),
- .we(sys_eim_wr),
-
- .address(addr_core_reg),
- .write_data(sys_write_data),
- .read_data(read_data_{core.instance_name}),
- .error(error_{core.instance_name})
- );
-
-
-"""
-
# Template used by TRNGCore.createInstance(); this is different enough
# from the generic template that it's (probably) clearer to have this
# separate.
-#
-# Should this also be checking sys_ena? Not obvious to me either way.
createInstance_template_TRNG = """\
//----------------------------------------------------------------
@@ -259,7 +236,7 @@ createInstance_template_TRNG = """\
{core.name} {core.instance_name}_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ {core.reset_pin},
.cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -353,6 +330,8 @@ endmodule
# Template for makefile snippet listing Verilog source files.
listVfiles_template = """\
+# NOTE: This file is generated; do not edit by hand.
+
vfiles +={vfiles}
"""
diff --git a/config/core_selector.v b/config/core_selector.v
index 4debd60..731b494 100644
--- a/config/core_selector.v
+++ b/config/core_selector.v
@@ -51,7 +51,7 @@ module core_selector
board_regs board_regs_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ .rst(sys_rst),
.cs(enable_board_regs & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -72,7 +72,7 @@ module core_selector
comm_regs comm_regs_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ .rst(sys_rst),
.cs(enable_comm_regs & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
diff --git a/config/core_vfiles.mk b/config/core_vfiles.mk
new file mode 100644
index 0000000..bd1c6d4
--- /dev/null
+++ b/config/core_vfiles.mk
@@ -0,0 +1,34 @@
+# NOTE: This file is generated; do not edit by hand.
+
+vfiles += \
+ $(CORE_TREE)/hash/sha256/src/rtl/sha256.v \
+ $(CORE_TREE)/hash/sha256/src/rtl/sha256_core.v \
+ $(CORE_TREE)/hash/sha256/src/rtl/sha256_k_constants.v \
+ $(CORE_TREE)/hash/sha256/src/rtl/sha256_w_mem.v \
+ $(CORE_TREE)/cipher/aes/src/rtl/aes.v \
+ $(CORE_TREE)/cipher/aes/src/rtl/aes_core.v \
+ $(CORE_TREE)/cipher/aes/src/rtl/aes_decipher_block.v \
+ $(CORE_TREE)/cipher/aes/src/rtl/aes_encipher_block.v \
+ $(CORE_TREE)/cipher/aes/src/rtl/aes_inv_sbox.v \
+ $(CORE_TREE)/cipher/aes/src/rtl/aes_key_mem.v \
+ $(CORE_TREE)/cipher/aes/src/rtl/aes_sbox.v \
+ $(CORE_TREE)/rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
+ $(CORE_TREE)/rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
+ $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc.v \
+ $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc_entropy.v \
+ $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
+ $(CORE_TREE)/rng/trng/src/rtl/trng.v \
+ $(CORE_TREE)/rng/trng/src/rtl/trng_csprng.v \
+ $(CORE_TREE)/rng/trng/src/rtl/trng_csprng_fifo.v \
+ $(CORE_TREE)/rng/trng/src/rtl/trng_mixer.v \
+ $(CORE_TREE)/math/modexp/src/rtl/adder.v \
+ $(CORE_TREE)/math/modexp/src/rtl/blockmem1r1w.v \
+ $(CORE_TREE)/math/modexp/src/rtl/blockmem2r1wptr.v \
+ $(CORE_TREE)/math/modexp/src/rtl/blockmem2r1w.v \
+ $(CORE_TREE)/math/modexp/src/rtl/blockmem2rptr1w.v \
+ $(CORE_TREE)/math/modexp/src/rtl/modexp.v \
+ $(CORE_TREE)/math/modexp/src/rtl/modexp_core.v \
+ $(CORE_TREE)/math/modexp/src/rtl/montprod.v \
+ $(CORE_TREE)/math/modexp/src/rtl/residue.v \
+ $(CORE_TREE)/math/modexp/src/rtl/shl.v \
+ $(CORE_TREE)/math/modexp/src/rtl/shr.v