diff options
author | Rob Austein <sra@hactrn.net> | 2015-09-27 18:58:10 -0400 |
---|---|---|
committer | Rob Austein <sra@hactrn.net> | 2015-09-27 18:58:10 -0400 |
commit | 0ef997a7567156ed271f36b64e077bd75c9e1798 (patch) | |
tree | 3bbdfb4c0dcb1a704130c89b1cba53e3993a9027 /config/core_selector.v | |
parent | cf8167215459811f8047f7c6d4f5972d924f6689 (diff) |
Wedge modexps6 into the addressing scheme. Adjust timing of other
cores. Tweak TRNG templates to support multiple instances, more for
consistency than than because we really expect multiple TRNGs.
Diffstat (limited to 'config/core_selector.v')
-rw-r--r-- | config/core_selector.v | 44 |
1 files changed, 34 insertions, 10 deletions
diff --git a/config/core_selector.v b/config/core_selector.v index 731b494..16d1a09 100644 --- a/config/core_selector.v +++ b/config/core_selector.v @@ -61,6 +61,10 @@ module core_selector .read_data(read_data_board_regs) ); + reg [31: 0] read_data_board_regs_reg; + always @(posedge sys_clk) + read_data_board_regs_reg <= read_data_board_regs; + //---------------------------------------------------------------- // COMM_REGS @@ -82,6 +86,10 @@ module core_selector .read_data(read_data_comm_regs) ); + reg [31: 0] read_data_comm_regs_reg; + always @(posedge sys_clk) + read_data_comm_regs_reg <= read_data_comm_regs; + //---------------------------------------------------------------- // SHA256 @@ -103,6 +111,10 @@ module core_selector .read_data(read_data_sha256) ); + reg [31: 0] read_data_sha256_reg; + always @(posedge sys_clk) + read_data_sha256_reg <= read_data_sha256; + //---------------------------------------------------------------- // AES @@ -124,6 +136,10 @@ module core_selector .read_data(read_data_aes) ); + reg [31: 0] read_data_aes_reg; + always @(posedge sys_clk) + read_data_aes_reg <= read_data_aes; + //---------------------------------------------------------------- // TRNG @@ -149,6 +165,10 @@ module core_selector .debug(debug) ); + reg [31: 0] read_data_trng_reg; + always @(posedge sys_clk) + read_data_trng_reg <= read_data_trng; + //---------------------------------------------------------------- // MODEXP @@ -170,6 +190,10 @@ module core_selector .read_data(read_data_modexp) ); + reg [31: 0] read_data_modexp_reg; + always @(posedge sys_clk) + read_data_modexp_reg <= read_data_modexp; + //---------------------------------------------------------------- @@ -185,52 +209,52 @@ module core_selector case (addr_core_num) CORE_ADDR_BOARD_REGS: begin - sys_read_data_mux = read_data_board_regs; + sys_read_data_mux = read_data_board_regs_reg; sys_error_mux = error_board_regs; end CORE_ADDR_COMM_REGS: begin - sys_read_data_mux = read_data_comm_regs; + sys_read_data_mux = read_data_comm_regs_reg; sys_error_mux = error_comm_regs; end CORE_ADDR_SHA256: begin - sys_read_data_mux = read_data_sha256; + sys_read_data_mux = read_data_sha256_reg; sys_error_mux = error_sha256; end CORE_ADDR_AES: begin - sys_read_data_mux = read_data_aes; + sys_read_data_mux = read_data_aes_reg; sys_error_mux = error_aes; end CORE_ADDR_TRNG: begin - sys_read_data_mux = read_data_trng; + sys_read_data_mux = read_data_trng_reg; sys_error_mux = error_trng; end CORE_ADDR_AVALANCHE_ENTROPY: begin - sys_read_data_mux = read_data_trng; + sys_read_data_mux = read_data_trng_reg; sys_error_mux = error_trng; end CORE_ADDR_ROSC_ENTROPY: begin - sys_read_data_mux = read_data_trng; + sys_read_data_mux = read_data_trng_reg; sys_error_mux = error_trng; end CORE_ADDR_TRNG_MIXER: begin - sys_read_data_mux = read_data_trng; + sys_read_data_mux = read_data_trng_reg; sys_error_mux = error_trng; end CORE_ADDR_TRNG_CSPRNG: begin - sys_read_data_mux = read_data_trng; + sys_read_data_mux = read_data_trng_reg; sys_error_mux = error_trng; end CORE_ADDR_MODEXP: begin - sys_read_data_mux = read_data_modexp; + sys_read_data_mux = read_data_modexp_reg; sys_error_mux = error_modexp; end |