Change reset to active-low.

1 files changed, 3 insertions, 3 deletions

diff --git a/common/rtl/novena_regs.v b/common/rtl/novena_regs.v
index eb89092..4edf028 100644
--- a/common/rtl/novena_regs.v
+++ b/common/rtl/novena_regs.v
@@ -42,7 +42,7 @@ module board_regs
   (
    // Clock and reset.
    input wire           clk,
-   input wire           rst,
+   input wire           reset_n,
 
    // Control.
    input wire           cs,
@@ -96,9 +96,9 @@ module board_regs
    //----------------------------------------------------------------
    // storage registers for mapping memory to core interface
    //----------------------------------------------------------------
-   always @ (posedge clk or posedge rst)
+   always @ (posedge clk or negedge reset_n)
      begin
-        if (rst)
+        if (!reset_n)
           begin
              reg_dummy <= {32{1'b0}};
           end