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authorRob Austein <sra@hactrn.net>2015-09-23 16:31:28 -0400
committerRob Austein <sra@hactrn.net>2015-09-23 16:31:28 -0400
commit026fc461d9791bc360036f1269d0f6d61c45d179 (patch)
treef1c86f833ac220c6e21a59d184558bf6e7a92789 /common/rtl
parent99c3749c85b85b4865c4baafdd16b2cbb3ac52f2 (diff)
Trailing whitespace cleanup.
Diffstat (limited to 'common/rtl')
-rw-r--r--common/rtl/lint-dummy.v14
-rw-r--r--common/rtl/novena_regs.v4
2 files changed, 9 insertions, 9 deletions
diff --git a/common/rtl/lint-dummy.v b/common/rtl/lint-dummy.v
index 9d4d2d3..5cf4b61 100644
--- a/common/rtl/lint-dummy.v
+++ b/common/rtl/lint-dummy.v
@@ -69,7 +69,7 @@ module FD (Q, C, D);
input C, D;
endmodule
-module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP);
+module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP);
parameter integer A0REG = 0;
parameter integer A1REG = 1;
parameter integer B0REG = 0;
@@ -83,11 +83,11 @@ module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA,
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter RSTTYPE = "SYNC";
- output [17:0] BCOUT;
- output CARRYOUT;
- output CARRYOUTF;
- output [35:0] M;
- output [47:0] P;
+ output [17:0] BCOUT;
+ output CARRYOUT;
+ output CARRYOUTF;
+ output [35:0] M;
+ output [47:0] P;
output [47:0] PCOUT;
input [17:0] A;
input [17:0] B;
@@ -110,7 +110,7 @@ module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA,
input RSTC;
input RSTCARRYIN;
input RSTD;
- input RSTM;
+ input RSTM;
input RSTOPMODE;
input RSTP;
endmodule
diff --git a/common/rtl/novena_regs.v b/common/rtl/novena_regs.v
index eb89092..6b52a80 100644
--- a/common/rtl/novena_regs.v
+++ b/common/rtl/novena_regs.v
@@ -86,13 +86,13 @@ module board_regs
wire [31 : 0] core_name0 = CORE_NAME0;
wire [31 : 0] core_name1 = CORE_NAME1;
wire [31 : 0] core_version = CORE_VERSION;
-
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = write_error | read_error;
-
+
//----------------------------------------------------------------
// storage registers for mapping memory to core interface
//----------------------------------------------------------------