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authorPaul Selkirk <pselkirk@isc.org>2015-03-17 13:49:30 +0100
committerPaul Selkirk <pselkirk@isc.org>2015-03-17 13:49:30 +0100
commit283bfbeeb7fb5767815c10ea98bb155638d4bfb3 (patch)
tree5929001d84e6ef964d1338c71b27418ad8a146bf /common/rtl/ipcore/coregen.cgp
parent21ef7967486b349d66703c13edfff58d5f13372a (diff)
Rearrange cores.
Diffstat (limited to 'common/rtl/ipcore/coregen.cgp')
-rw-r--r--common/rtl/ipcore/coregen.cgp9
1 files changed, 9 insertions, 0 deletions
diff --git a/common/rtl/ipcore/coregen.cgp b/common/rtl/ipcore/coregen.cgp
new file mode 100644
index 0000000..8bc2e70
--- /dev/null
+++ b/common/rtl/ipcore/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false