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| author | Paul Selkirk <paul@psgd.org> | 2015-11-12 15:41:48 -0500 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-11-12 15:41:48 -0500 |
| commit | 4cfd0c3dbe688960f6b7e7285b7a14cebb1586a3 (patch) | |
| tree | 71652936b7d220ca9418975c64c2ae34ba301437 /common/rtl/clkmgr_dcm.v | |
| parent | c88137ebab8561777b5ffb3ae045960990b2760d (diff) | |
| parent | 1eccd3c5a72503ac89df0708c42d7f0a3177c3ac (diff) | |
Merge branch 'activelow'
Diffstat (limited to 'common/rtl/clkmgr_dcm.v')
| -rw-r--r-- | common/rtl/clkmgr_dcm.v | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/common/rtl/clkmgr_dcm.v b/common/rtl/clkmgr_dcm.v index 5651b93..7c851f1 100644 --- a/common/rtl/clkmgr_dcm.v +++ b/common/rtl/clkmgr_dcm.v @@ -51,13 +51,14 @@ module clkmgr_dcm // // Parameters // - parameter CLK_OUT_MUL = 2; - parameter CLK_OUT_DIV = 2; + parameter CLK_OUT_MUL = 2; // multiply factor for output clock frequency (2..32) + parameter CLK_OUT_DIV = 2; // divide factor for output clock frequency (1..32) // // DCM_SP // + /* Xilinx-specific primitive. */ wire dcm_clk_0; wire dcm_clk_feedback; wire dcm_clk_fx; @@ -121,6 +122,7 @@ module clkmgr_dcm // // Feedback // + /* DCM_SP requires BUFG primitive in its feedback path. */ BUFG BUFG_feedback ( .I (dcm_clk_0), @@ -130,6 +132,7 @@ module clkmgr_dcm // // Output Buffer // + /* Connect system clock to global clocking network. */ BUFG BUFG_output ( .I (dcm_clk_fx), |