Move novena_regs.v to common, fix to match other register read/write blocks.

5 files changed, 60 insertions, 45 deletions

diff --git a/i2c/rtl/novena_regs.v b/common/rtl/novena_regs.v
index f14e113..716f650 100644
--- a/i2c/rtl/novena_regs.v
+++ b/common/rtl/novena_regs.v
@@ -66,60 +66,63 @@ module board_regs
    localparam CORE_NAME1   = 32'h20202020;  // "    "
    localparam CORE_VERSION = 32'h302e3130;  // "0.10"
 
-
    //----------------------------------------------------------------
-   // Wires.
+   // Registers.
    //----------------------------------------------------------------
    reg [31: 0]          tmp_read_data;
 
    // dummy register to check that you can actually write something
-   reg [31: 0] 		reg_dummy;
+   reg [31: 0]          reg_dummy;
 
+   //----------------------------------------------------------------
+   // Wires.
+   //----------------------------------------------------------------
+   wire [31 : 0]               core_name0   = CORE_NAME0;
+   wire [31 : 0]               core_name1   = CORE_NAME1;
+   wire [31 : 0]               core_version = CORE_VERSION;
    
    //----------------------------------------------------------------
    // Concurrent connectivity for ports etc.
    //----------------------------------------------------------------
    assign read_data = tmp_read_data;
    
-
    //----------------------------------------------------------------
-   // Access Handler
+   // storage registers for mapping memory to core interface
    //----------------------------------------------------------------
-   always @(posedge clk)
-     //
-     if (rst)
-       reg_dummy <= {32{1'b0}};
-     else if (cs) begin
-        //
-        if (we) begin
-           //
-           // WRITE handler
-           //
-           case (address)
-             ADDR_DUMMY_REG:
-               reg_dummy        <= write_data;
-           endcase
-           //
-        end else begin
-           //
-           // READ handler
-           //
-           case (address)
-             ADDR_CORE_NAME0:
-               tmp_read_data <= CORE_NAME0;
-             ADDR_CORE_NAME1:
-               tmp_read_data <= CORE_NAME1;
-             ADDR_CORE_VERSION:
-               tmp_read_data <= CORE_VERSION;
-             ADDR_DUMMY_REG:
-               tmp_read_data <= reg_dummy;
-             //
-             default:
-               tmp_read_data <= {32{1'b0}};  // read non-existent locations as zeroes
-           endcase
-           //
-        end
-        //
+   always @ (posedge clk or posedge rst)
+     begin
+        if (rst)
+          begin
+             reg_dummy <= {32{1'b0}};
+          end
+        else if (cs && we)
+          begin
+             // write operations
+             case (address)
+               ADDR_DUMMY_REG:
+                 reg_dummy <= write_data;
+             endcase
+          end
+     end
+
+   always @*
+     begin
+        tmp_read_data = 32'h00000000;
+
+        if (cs && !we)
+          begin
+             // read operations
+             case (address)
+               ADDR_CORE_NAME0:
+                 tmp_read_data = core_name0;
+               ADDR_CORE_NAME1:
+                 tmp_read_data = core_name1;
+               ADDR_CORE_VERSION:
+                 tmp_read_data = core_version;
+               ADDR_DUMMY_REG:
+                 tmp_read_data = reg_dummy;
+             endcase
+          end
      end
 
 endmodule
diff --git a/eim/build/Makefile b/eim/build/Makefile
index b677364..e93b05f 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -9,7 +9,7 @@ ucf = ../ucf/novena_eim.ucf
 
 vfiles = \
 	../rtl/novena_eim.v \
-	../rtl/novena_regs.v \
+	../../common/rtl/novena_regs.v \
 	../../common/rtl/novena_clkmgr.v \
 	../../common/rtl/ipcore/clkmgr_dcm.v \
 	../../../common/core_selector/src/rtl/core_selector.v \
diff --git a/eim/iseconfig/novena_eim.xise b/eim/iseconfig/novena_eim.xise
index b22ae9f..b29633e 100644
--- a/eim/iseconfig/novena_eim.xise
+++ b/eim/iseconfig/novena_eim.xise
@@ -19,7 +19,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
     </file>
-    <file xil_pn:name="../rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../common/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
diff --git a/i2c/build/Makefile b/i2c/build/Makefile
index 3959c4f..d881820 100644
--- a/i2c/build/Makefile
+++ b/i2c/build/Makefile
@@ -9,7 +9,7 @@ ucf = ../ucf/novena_i2c.ucf
 
 vfiles = \
 	../rtl/novena_i2c.v \
-	../rtl/novena_regs.v \
+	../../common/rtl/novena_regs.v \
 	../../common/rtl/novena_clkmgr.v \
 	../../common/rtl/ipcore/clkmgr_dcm.v \
 	../../../common/core_selector/src/rtl/core_selector.v \
@@ -31,6 +31,18 @@ vfiles = \
 	../../../../hash/sha512/src/rtl/sha512_core.v \
 	../../../../hash/sha512/src/rtl/sha512_h_constants.v \
 	../../../../hash/sha512/src/rtl/sha512_k_constants.v \
-	../../../../hash/sha512/src/rtl/sha512_w_mem.v
+	../../../../hash/sha512/src/rtl/sha512_w_mem.v \
+	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
+	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
+	../../../../rng/rosc_entropy/src/rtl/rosc.v \
+	../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
+	../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
+	../../../../rng/trng/src/rtl/trng.v \
+	../../../../rng/trng/src/rtl/trng_csprng.v \
+	../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
+	../../../../rng/trng/src/rtl/trng_mixer.v \
+	../../../../cipher/chacha/src/rtl/chacha.v \
+	../../../../cipher/chacha/src/rtl/chacha_core.v \
+	../../../../cipher/chacha/src/rtl/chacha_qr.v
 
 include xilinx.mk
diff --git a/i2c/iseconfig/novena_i2c.xise b/i2c/iseconfig/novena_i2c.xise
index 719e157..934ca05 100644
--- a/i2c/iseconfig/novena_i2c.xise
+++ b/i2c/iseconfig/novena_i2c.xise
@@ -19,7 +19,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
-    <file xil_pn:name="../rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../common/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>