diff options
| author | Paul Selkirk <paul@psgd.org> | 2015-06-18 13:46:16 -0400 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-06-18 13:46:16 -0400 |
| commit | 6fde50c9dd78be8662f7e84833d5c696b087ab9a (patch) | |
| tree | e70ec1a2f9b334b09cbe7e7d1bc865a984f56c4d | |
| parent | 80205a9ff9a8b4da93aa74d7b73f16832682384a (diff) | |
add support for verilator linting
| -rw-r--r-- | common/rtl/lint-dummy.v | 64 | ||||
| -rw-r--r-- | eim/build/Makefile | 3 | ||||
| -rw-r--r-- | i2c/build/Makefile | 3 |
3 files changed, 70 insertions, 0 deletions
diff --git a/common/rtl/lint-dummy.v b/common/rtl/lint-dummy.v new file mode 100644 index 0000000..9016622 --- /dev/null +++ b/common/rtl/lint-dummy.v @@ -0,0 +1,64 @@ +// dummy modules for Xilinx IP for verilator linting + +// The module definitions are ganked from +// /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims. It would be easier +// to run verilator with -I for that directory, but verilator really +// doesn't like the Xilinx code. + +/*verilator lint_off UNDRIVEN*/ +/*verilator lint_off UNUSED*/ + +module DCM_SP ( + CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, + CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, + CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST); +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DSS_MODE = "NONE"; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hC080; +parameter integer PHASE_SHIFT = 0; +parameter STARTUP_WAIT = "FALSE"; +output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; +output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE; +output [7:0] STATUS; +input CLKFB, CLKIN, DSSEN; +input PSCLK, PSEN, PSINCDEC, RST; +endmodule + +module BUFG (O, I); + output O; + input I; +endmodule + +module IBUFGDS (O, I, IB); + output O; + input I, IB; +endmodule + +module IOBUF (O, IO, I, T); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + output O; + inout IO; + input I, T; +endmodule + +module FDCE (Q, C, CE, CLR, D); + parameter INIT = 1'b0; + output Q; + input C, CE, CLR, D; +endmodule diff --git a/eim/build/Makefile b/eim/build/Makefile index 7bb4ffd..5fd3f2a 100644 --- a/eim/build/Makefile +++ b/eim/build/Makefile @@ -69,3 +69,6 @@ vfiles = \ ../../../../math/modexp/src/rtl/shr32.v include xilinx.mk + +lint: + verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v diff --git a/i2c/build/Makefile b/i2c/build/Makefile index d881820..b383078 100644 --- a/i2c/build/Makefile +++ b/i2c/build/Makefile @@ -46,3 +46,6 @@ vfiles = \ ../../../../cipher/chacha/src/rtl/chacha_qr.v include xilinx.mk + +lint: + verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v |