From cce47a9367701af12950a6b6dccb5a0a4da60709 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Wed, 15 Aug 2018 17:23:25 -0400 Subject: Add support for Joachim's keywrap core. --- config/core.cfg | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'config') diff --git a/config/core.cfg b/config/core.cfg index 222a8e0..adce434 100644 --- a/config/core.cfg +++ b/config/core.cfg @@ -90,12 +90,16 @@ cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384 # super-size it cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes aes aes modexp modexp modexp ecdsa256 ecdsa256 ecdsa256 ecdsa384 ecdsa384 ecdsa384 +[project keywrap] +# for testing Joachim's keywrap core with RSA signing +cores = mkmif sha256 aes trng modexp keywrap + # [core] sections # # vfiles: A list of Verilog files to include in the vfiles list when -# including a particular core. All (optional) cores must have a -# vfiles option, so that the configuration program knows what to put -# into core_vfiles.mk. +# including a particular core. File paths are relative to the cores/ +# directory. All (optional) cores must have a vfiles option, so that the +# configuration program knows what to put into core_vfiles.mk. # # requires: A list of other cores whose vfiles must be loaded to build # this core. This has no effect on the generated core_selector.v @@ -214,6 +218,7 @@ vfiles = math/modexpa7/src/rtl/pe/modexpa7_subtractor32.v math/modexpa7/src/rtl/pe/modexpa7_systolic_pe.v math/modexpa7/src/rtl/util/bram_1rw_readfirst.v + math/ecdsalib/rtl/util/bram_1rw_1ro_readfirst.v [core modexps6] # ModExp for Xilinx Spartan-6 @@ -374,3 +379,14 @@ vfiles = math/ecdsalib/rtl/multiword/mw_comparator.v math/ecdsalib/rtl/multiword/mw_mover.v math/ecdsalib/rtl/util/bram_1rw_1ro_readfirst.v + +[core keywrap] +# Joachim's experimental AES-keywrap core +requires = aes +block memory = yes +error wire = yes +module name = keywrap +vfiles = + ../user/js/keywrap/src/rtl/keywrap.v + ../user/js/keywrap/src/rtl/keywrap_core.v + ../user/js/keywrap/src/rtl/keywrap_mem.v -- cgit v1.2.3 From 21945dab1118388d3620a954b0393b9b79f23c39 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Thu, 23 Aug 2018 16:19:40 -0400 Subject: core.cfg [project keywrap]: We want two modexp cores for parallel CRT (and we fail badly if we don't get them). Also add ecdsa cores, so we can meaningfully compare results vs stock bitstream. --- config/core.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'config') diff --git a/config/core.cfg b/config/core.cfg index adce434..2194733 100644 --- a/config/core.cfg +++ b/config/core.cfg @@ -92,7 +92,7 @@ cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes [project keywrap] # for testing Joachim's keywrap core with RSA signing -cores = mkmif sha256 aes trng modexp keywrap +cores = mkmif sha256 aes trng modexp modexp ecdsa256 ecdsa384 keywrap # [core] sections # -- cgit v1.2.3 From 165585268fd95a80d848d4a4be6b965cda1088cc Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 11 Sep 2018 18:55:54 -0400 Subject: Track Joachim's latest keywrap core - unroll bank-switched memory into a number of core register blocks. --- config/core.cfg | 3 ++- config/core_config.py | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'config') diff --git a/config/core.cfg b/config/core.cfg index 2194733..67497e6 100644 --- a/config/core.cfg +++ b/config/core.cfg @@ -80,7 +80,7 @@ cores = mkmif [project rsa] # RSA signing and verification. This is as much as will fit on the # Novena's Spartan-6 FPGA. -cores = sha256 aes trng modexp +cores = sha256 aes trng modexp mkmif [project hsm] # Make me one with everything, except we want two modexp cores for parallel CRT @@ -383,6 +383,7 @@ vfiles = [core keywrap] # Joachim's experimental AES-keywrap core requires = aes +core blocks = 32 block memory = yes error wire = yes module name = keywrap diff --git a/config/core_config.py b/config/core_config.py index 4033279..d84f8f1 100755 --- a/config/core_config.py +++ b/config/core_config.py @@ -226,7 +226,7 @@ class Core(object): self.block_max = self.blocks - 1 if self.blocks > 1: try: - self.block_bits = {4:2, 8:3, 16:4}[self.blocks] + self.block_bits = {4:2, 8:3, 16:4, 32:5}[self.blocks] except KeyError: raise ValueError, "In [{}]: unexpected value \"core blocks = {}\"".format(self.cfg_section, self.blocks) self.block_bit_max = self.block_bits - 1 -- cgit v1.2.3 From 3ec87a9a5f101099249496be576c6fb8f0d283a5 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Wed, 15 Aug 2018 17:23:25 -0400 Subject: Add support for Joachim's keywrap core. --- config/core.cfg | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'config') diff --git a/config/core.cfg b/config/core.cfg index d6de1fa..8a7d252 100644 --- a/config/core.cfg +++ b/config/core.cfg @@ -86,12 +86,16 @@ cores = sha256 aes trng modexp # Make me one with everything, except we want two modexp cores for parallel CRT cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384 +[project keywrap] +# for testing Joachim's keywrap core with RSA signing +cores = mkmif sha256 aes trng modexp keywrap + # [core] sections # # vfiles: A list of Verilog files to include in the vfiles list when -# including a particular core. All (optional) cores must have a -# vfiles option, so that the configuration program knows what to put -# into core_vfiles.mk. +# including a particular core. File paths are relative to the cores/ +# directory. All (optional) cores must have a vfiles option, so that the +# configuration program knows what to put into core_vfiles.mk. # # requires: A list of other cores whose vfiles must be loaded to build # this core. This has no effect on the generated core_selector.v @@ -325,3 +329,14 @@ vfiles = lib/modular/modular_adder.v lib/modular/modular_subtractor.v lib/lowlevel/artix7/dsp48e1_wrapper.v + +[core keywrap] +# Joachim's experimental AES-keywrap core +requires = aes +block memory = yes +error wire = yes +module name = keywrap +vfiles = + ../user/js/keywrap/src/rtl/keywrap.v + ../user/js/keywrap/src/rtl/keywrap_core.v + ../user/js/keywrap/src/rtl/keywrap_mem.v -- cgit v1.2.3 From 1c4ba32f4190c0a4b501077225762598ba9d4821 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Thu, 23 Aug 2018 16:19:40 -0400 Subject: core.cfg [project keywrap]: We want two modexp cores for parallel CRT (and we fail badly if we don't get them). Also add ecdsa cores, so we can meaningfully compare results vs stock bitstream. --- config/core.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'config') diff --git a/config/core.cfg b/config/core.cfg index 8a7d252..12362c6 100644 --- a/config/core.cfg +++ b/config/core.cfg @@ -88,7 +88,7 @@ cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384 [project keywrap] # for testing Joachim's keywrap core with RSA signing -cores = mkmif sha256 aes trng modexp keywrap +cores = mkmif sha256 aes trng modexp modexp ecdsa256 ecdsa384 keywrap # [core] sections # -- cgit v1.2.3 From 050237cf05b7bef2887a53b1dba1f6d95e2759ec Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 11 Sep 2018 18:55:54 -0400 Subject: Track Joachim's latest keywrap core - unroll bank-switched memory into a number of core register blocks. --- config/core.cfg | 3 ++- config/core_config.py | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'config') diff --git a/config/core.cfg b/config/core.cfg index 12362c6..70b86ab 100644 --- a/config/core.cfg +++ b/config/core.cfg @@ -80,7 +80,7 @@ cores = mkmif [project rsa] # RSA signing and verification. This is as much as will fit on the # Novena's Spartan-6 FPGA. -cores = sha256 aes trng modexp +cores = sha256 aes trng modexp mkmif [project hsm] # Make me one with everything, except we want two modexp cores for parallel CRT @@ -333,6 +333,7 @@ vfiles = [core keywrap] # Joachim's experimental AES-keywrap core requires = aes +core blocks = 32 block memory = yes error wire = yes module name = keywrap diff --git a/config/core_config.py b/config/core_config.py index 4033279..d84f8f1 100755 --- a/config/core_config.py +++ b/config/core_config.py @@ -226,7 +226,7 @@ class Core(object): self.block_max = self.blocks - 1 if self.blocks > 1: try: - self.block_bits = {4:2, 8:3, 16:4}[self.blocks] + self.block_bits = {4:2, 8:3, 16:4, 32:5}[self.blocks] except KeyError: raise ValueError, "In [{}]: unexpected value \"core blocks = {}\"".format(self.cfg_section, self.blocks) self.block_bit_max = self.block_bits - 1 -- cgit v1.2.3