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-rw-r--r--extra/reset_replicator.v93
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+//======================================================================
+//
+// reset_replicator.v
+// ------------------
+//
+// Generates localized copies of the system-wide reset so that each core can
+// have its own copy. This way there's more room for the placer to do its job.
+//
+// Author: Pavel Shatov
+// Copyright (c) 2016, 2018-2019 NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module reset_replicator
+(
+ sys_clk_in,
+ sys_rst_n_in,
+ sys_rst_n_out
+);
+
+ //
+ // Parameters
+ //
+ parameter integer SHREG_WIDTH = 8;
+ parameter integer FANOUT_WIDTH = 8;
+
+ //
+ // Ports
+ //
+ input sys_clk_in;
+ input sys_rst_n_in;
+ output [FANOUT_WIDTH-1:0] sys_rst_n_out;
+
+ //
+ // Internals
+ //
+ wire [FANOUT_WIDTH-1:0] sys_rst_int;
+
+ //
+ // Localized Reset Replication
+ //
+ genvar i;
+ generate for (i=0; i<FANOUT_WIDTH; i=i+1)
+ //
+ begin : gen_sys_rst_n_out
+ //
+ LUT1 #(.INIT(2'b01)) LUT1_inst
+ ( .I0(sys_rst_n_in),
+ .O(sys_rst_int[i])
+ );
+ //
+ (* SHREG_EXTRACT="NO" *)
+ (* EQUIVALENT_REGISTER_REMOVAL="NO" *)
+ reg [SHREG_WIDTH-1:0] sys_rst_n_shreg_copy = {SHREG_WIDTH{1'b0}};
+ //
+ always @(posedge sys_clk_in or posedge sys_rst_int[i])
+ //
+ if (sys_rst_int[i]) sys_rst_n_shreg_copy <= {SHREG_WIDTH{1'b0}};
+ else sys_rst_n_shreg_copy <= {sys_rst_n_shreg_copy[SHREG_WIDTH-2:0], 1'b1};
+ //
+ assign sys_rst_n_out[i] = sys_rst_n_shreg_copy[SHREG_WIDTH-1];
+ //
+ end
+ //
+ endgenerate
+
+endmodule