Added reset replicator module. Details below.

Due to security reasons, we must use async reset for sensitive parts of the
design. In short, if the system clock is stopped, which is definitely an
abnormal situation, sync reset won't let us to wipe secret information and a
potential attacker can then try to steal it. Async reset is generally
discouraged in an FPGA, since it's very often a highway to failed timing, but
we use it knowingly. Now another catch is that our convention is to use
active-low reset signal polarity, since we might go for an ASIC in the future
and that's what you would use there. The problem is that currently we use an
FPGA, where most of the primitives have active-high reset ports. ISE will
throw in an invertor LUT during synthesis and then route all the reset signals
from this LUT. What you get is a "root" invertor LUT, that effectively resets
an entire design. No wonder global placement takes hours. Moreover, this extra
LUT doesn't allow easy replication of the reset signal. This special replicator
module manually instantiates as many invertor LUTs as necessary inside of a
generate loop. Luckily, manually instantiated CLB primitives aren't optimized
away during synthesis (thanks, Xilinx, seriously). Those invertor LUTs are then
followed by asynchronous active-low localized reset generators, that also can't
be optimized away.

1 files changed, 93 insertions, 0 deletions

diff --git a/extra/reset_replicator.v b/extra/reset_replicator.v
new file mode 100644
index 0000000..ccb704b
--- /dev/null
+++ b/extra/reset_replicator.v
@@ -0,0 +1,93 @@
+//======================================================================
+//
+// reset_replicator.v
+// ------------------
+//
+// Generates localized copies of the system-wide reset so that each core can
+// have its own copy. This way there's more room for the placer to do its job.
+//
+// Author: Pavel Shatov
+// Copyright (c) 2016, 2018-2019 NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module reset_replicator
+(
+    sys_clk_in,
+    sys_rst_n_in,
+    sys_rst_n_out
+);
+
+    //
+    // Parameters
+    //
+    parameter integer SHREG_WIDTH  = 8;
+    parameter integer FANOUT_WIDTH = 8;
+
+    //
+    // Ports
+    //
+    input                     sys_clk_in;
+    input                     sys_rst_n_in;
+    output [FANOUT_WIDTH-1:0] sys_rst_n_out;
+
+    //
+    // Internals
+    //
+    wire [FANOUT_WIDTH-1:0] sys_rst_int;
+
+    //
+    // Localized Reset Replication
+    //
+    genvar i;
+    generate for (i=0; i<FANOUT_WIDTH; i=i+1)
+        //
+        begin : gen_sys_rst_n_out
+            //
+            LUT1 #(.INIT(2'b01)) LUT1_inst
+            (   .I0(sys_rst_n_in),
+                .O(sys_rst_int[i])
+            );
+            //
+            (* SHREG_EXTRACT="NO" *)
+            (* EQUIVALENT_REGISTER_REMOVAL="NO" *)
+            reg [SHREG_WIDTH-1:0] sys_rst_n_shreg_copy = {SHREG_WIDTH{1'b0}};
+            //
+            always @(posedge sys_clk_in or posedge sys_rst_int[i])
+            //
+                if (sys_rst_int[i]) sys_rst_n_shreg_copy <= {SHREG_WIDTH{1'b0}};
+                else                sys_rst_n_shreg_copy <= {sys_rst_n_shreg_copy[SHREG_WIDTH-2:0], 1'b1};
+            //
+            assign sys_rst_n_out[i] = sys_rst_n_shreg_copy[SHREG_WIDTH-1];
+            //
+        end
+        //
+    endgenerate
+
+endmodule