diff options
author | Paul Selkirk <paul@psgd.org> | 2015-03-25 01:04:59 -0400 |
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committer | Paul Selkirk <paul@psgd.org> | 2015-03-25 01:04:59 -0400 |
commit | 989c112328f293ca1dfdea2da08afc79e960e841 (patch) | |
tree | 1396d37dea3b114f2b73288b9a5ad37500d586fa /core_selector/src/rtl/core_selector.v | |
parent | 63c5dae7baada6cc8f459f23d5840c56250d8bf7 (diff) |
integrate trng into core_selector framework
Diffstat (limited to 'core_selector/src/rtl/core_selector.v')
-rw-r--r-- | core_selector/src/rtl/core_selector.v | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v index 1cd1d94..a18717a 100644 --- a/core_selector/src/rtl/core_selector.v +++ b/core_selector/src/rtl/core_selector.v @@ -44,11 +44,15 @@ module core_selector input wire sys_clk, input wire sys_rst, + input wire noise, + input wire [16: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, output wire [31: 0] sys_read_data, - input wire [31: 0] sys_write_data + input wire [31: 0] sys_write_data, + + output wire [7 : 0] debug ); @@ -166,6 +170,8 @@ module core_selector .sys_clk(sys_clk), .sys_rst(sys_rst), + .noise(noise), + .sys_ena(segment_enable_rngs), // only enable active selector .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here, @@ -175,7 +181,9 @@ module core_selector .sys_eim_rd(sys_eim_rd), .sys_write_data(sys_write_data), - .sys_read_data(segment_rngs_read_data) // output from RNGS segment + .sys_read_data(segment_rngs_read_data), // output from RNGS segment + + .debug(debug) ); |