Added reset replicator module. Details below.

Due to security reasons, we must use async reset for sensitive parts of the
design. In short, if the system clock is stopped, which is definitely an
abnormal situation, sync reset won't let us to wipe secret information and a
potential attacker can then try to steal it. Async reset is generally
discouraged in an FPGA, since it's very often a highway to failed timing, but
we use it knowingly. Now another catch is that our convention is to use
active-low reset signal polarity, since we might go for an ASIC in the future
and that's what you would use there. The problem is that currently we use an
FPGA, where most of the primitives have active-high reset ports. ISE will
throw in an invertor LUT during synthesis and then route all the reset signals
from this LUT. What you get is a "root" invertor LUT, that effectively resets
an entire design. No wonder global placement takes hours. Moreover, this extra
LUT doesn't allow easy replication of the reset signal. This special replicator
module manually instantiates as many invertor LUTs as necessary inside of a
generate loop. Luckily, manually instantiated CLB primitives aren't optimized
away during synthesis (thanks, Xilinx, seriously). Those invertor LUTs are then
followed by asynchronous active-low localized reset generators, that also can't
be optimized away.

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