integrate trng into core_selector framework

3 files changed, 40 insertions, 123 deletions

diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v
index 1cd1d94..a18717a 100644
--- a/core_selector/src/rtl/core_selector.v
+++ b/core_selector/src/rtl/core_selector.v
@@ -44,11 +44,15 @@ module core_selector
    input wire          sys_clk,
    input wire          sys_rst,
 
+   input wire          noise, 
+
    input wire [16: 0]  sys_eim_addr,
    input wire          sys_eim_wr,
    input wire          sys_eim_rd,
    output wire [31: 0] sys_read_data,
-   input wire [31: 0]  sys_write_data
+   input wire [31: 0]  sys_write_data,
+
+   output wire [7 : 0] debug
    );
    
    
@@ -166,6 +170,8 @@ module core_selector
       .sys_clk(sys_clk),
       .sys_rst(sys_rst),
 
+      .noise(noise),
+
       .sys_ena(segment_enable_rngs),            // only enable active selector
 
       .sys_eim_addr(addr_segment_int),          // we only connect 14 lower bits of address here,
@@ -175,7 +181,9 @@ module core_selector
       .sys_eim_rd(sys_eim_rd),          
 
       .sys_write_data(sys_write_data),
-      .sys_read_data(segment_rngs_read_data)    // output from RNGS segment
+      .sys_read_data(segment_rngs_read_data),    // output from RNGS segment
+
+      .debug(debug)
       );
    
    
diff --git a/core_selector/src/rtl/global_selector.v b/core_selector/src/rtl/global_selector.v
index 993f237..25cad4e 100644
--- a/core_selector/src/rtl/global_selector.v
+++ b/core_selector/src/rtl/global_selector.v
@@ -106,69 +106,6 @@ module global_selector
    
    
    //----------------------------------------------------------------
-   // SHA-1
-   //----------------------------------------------------------------
-   `ifdef USE_CORE_SHA1
-   wire [31: 0]         read_data_sha1;
-   wire                 enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
-   sha1 sha1_inst
-     (
-      .clk(sys_clk),
-      .reset_n(~sys_rst),
-
-      .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
-      .we(sys_eim_wr),
-
-      .address(addr_core_reg),
-      .write_data(sys_write_data),
-      .read_data(read_data_sha1)
-      );
-   `endif
-   
-   
-   //----------------------------------------------------------------
-   // SHA-256
-   //----------------------------------------------------------------
-   `ifdef USE_CORE_SHA256
-   wire [31: 0]         read_data_sha256;
-   wire                 enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
-   sha256 sha256_inst
-     (
-      .clk(sys_clk),
-      .reset_n(~sys_rst),
-
-      .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
-      .we(sys_eim_wr),
-
-      .address(addr_core_reg),
-      .write_data(sys_write_data),
-      .read_data(read_data_sha256)
-      );
-   `endif
-   
-   
-   //----------------------------------------------------------------
-   // SHA-512
-   //----------------------------------------------------------------
-   `ifdef USE_CORE_SHA512
-   wire [31: 0]         read_data_sha512;
-   wire                 enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
-   sha512 sha512_inst
-     (
-      .clk(sys_clk),
-      .reset_n(~sys_rst),
-
-      .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
-      .we(sys_eim_wr),
-
-      .address(addr_core_reg),
-      .write_data(sys_write_data),
-      .read_data(read_data_sha512)
-      );
-   `endif
-   
-   
-   //----------------------------------------------------------------
    // Output (Read Data) Multiplexor
    //----------------------------------------------------------------
    reg [31: 0]          sys_read_data_mux;
diff --git a/core_selector/src/rtl/rng_selector.v b/core_selector/src/rtl/rng_selector.v
index d88fe82..3a0bd73 100644
--- a/core_selector/src/rtl/rng_selector.v
+++ b/core_selector/src/rtl/rng_selector.v
@@ -41,69 +41,41 @@
 
 module rng_selector
   (
-   input wire           sys_clk,
-   input wire           sys_rst,
-   input wire           sys_ena,
+   input wire 		sys_clk,
+   input wire 		sys_rst,
 
-   input wire [13: 0]   sys_eim_addr,
-   input wire           sys_eim_wr,
-   input wire           sys_eim_rd,
+   input wire		noise,
+
+   input wire 		sys_ena,
+   input wire [13: 0] 	sys_eim_addr,
+   input wire 		sys_eim_wr,
+   input wire 		sys_eim_rd,
    output wire [31 : 0] sys_read_data,
-   input wire [31 : 0]  sys_write_data
+   input wire [31 : 0] 	sys_write_data,
+
+   output wire [7 : 0] 	debug
    );
 
-   
-   //
-   // Output Register
-   //
-   reg [31: 0]          tmp_read_data;
-   assign sys_read_data = tmp_read_data;
-   
 
-   /* So far we have no RNG cores, let's make some dummy 32-bit registers here
-    * to prevent ISE from complaining that we don't use input ports.
-    */
-   
-   reg [31: 0]          reg_dummy_first;
-   reg [31: 0]          reg_dummy_second;
-   reg [31: 0]          reg_dummy_third;
-   
-   always @(posedge sys_clk)
-     //
-     if (sys_rst) begin
-        reg_dummy_first  <= {8{4'hA}};
-        reg_dummy_second <= {8{4'hB}};
-        reg_dummy_third  <= {8{4'hC}};
-     end else if (sys_ena) begin
-        //
-        if (sys_eim_wr) begin
-           //
-           // WRITE handler
-           //
-           case (sys_eim_addr)
-             14'd0: reg_dummy_first     <= sys_write_data;
-             14'd1: reg_dummy_second    <= sys_write_data;
-             14'd2: reg_dummy_third     <= sys_write_data;
-           endcase
-           //
-        end
-        //
-        if (sys_eim_rd) begin
-           //
-           // READ handler
-           //
-           case (sys_eim_addr)
-             14'd0: tmp_read_data       <= reg_dummy_first;
-             14'd1: tmp_read_data       <= reg_dummy_second;
-             14'd2: tmp_read_data       <= reg_dummy_third;
-             //
-             default:
-               tmp_read_data    <= {32{1'b0}};  // read non-existent locations as zeroes
-           endcase
-           //
-        end
-        //
-     end
+   // This is a pass-through to trng.v, which instantiates and muxes the
+   // entropy sources, mixer, and csprng.
+
+   trng trng_inst
+     (
+      .clk(sys_clk),
+      .reset_n(~sys_rst),
+
+      .avalanche_noise(noise),
+
+      .cs(sys_ena & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(sys_eim_addr[11:0]),
+      .write_data(sys_write_data),
+      .read_data(sys_read_data),
+
+      .debug(debug)
+      );
 
 endmodule