rtl/bench/tb_clkmgr.v


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`timescale 1ns / 1ps

module tb_clkmgr;

    // Input
	reg fmc_clk = 1'b0;

    // Clock
    always #11.111 fmc_clk = ~fmc_clk;

    // Outputs
    wire io_clk;
	wire sys_clk;
	wire sys_rst_n;
    wire core_clk;

    // Internals
    reg fmc_clk_inhibit = 1'b0;

	// UUT
	alpha_clkmgr uut
    (
        .fmc_clk(fmc_clk & ~fmc_clk_inhibit),
        .io_clk(io_clk),
		.sys_clk(sys_clk), 
		.sys_rst_n(sys_rst_n),
        .core_clk(core_clk)
	);
    
    // Script
    initial begin
        #399000;
        fmc_clk_inhibit = 1'b1;
        #1000;
        fmc_clk_inhibit = 1'b0;
    end
      
endmodule