set_input_delay -clock [get_clocks clk_fmc] -min 10.0 [get_ports {fmc_d[*]}]
set_input_delay -clock [get_clocks clk_fmc] -max 14.8 [get_ports {fmc_d[*]}]

set_input_delay -clock [get_clocks clk_fmc] -min -1.0 [get_ports {fmc_a[*]}]
set_input_delay -clock [get_clocks clk_fmc] -max 12.3 [get_ports {fmc_a[*]}]

set_input_delay -clock [get_clocks clk_fmc] -min  4.0 [get_ports {fmc_ne1 fmc_nl fmc_nwe}]
set_input_delay -clock [get_clocks clk_fmc] -max 12.8 [get_ports {fmc_ne1 fmc_nl fmc_nwe}]

set_multicycle_path -from [get_cells {cores/reg_read_data_*[*]}]        -to [get_cells {cores/pipe_read_data_*[*]}] -setup 2
set_multicycle_path -from [get_cells {cores/addr_core_num_dly2_reg[*]}] -to [get_cells {cores/pipe_read_data_*[*]}] -setup 2

set_multicycle_path -from [get_cells {cores/reg_read_data_*[*]}]        -to [get_cells {cores/pipe_read_data_*[*]}] -hold 1
set_multicycle_path -from [get_cells {cores/addr_core_num_dly2_reg[*]}] -to [get_cells {cores/pipe_read_data_*[*]}] -hold 1

set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets cores/trng_inst/entropy2/core/oscillators[0].rosc_array/dout_new]