From 7bf84ba5628678abc9d9ffa58c639eca7f3e095b Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 21 Jan 2020 15:43:40 +0300 Subject: Testbench for the new clock manager. --- rtl/bench/tb_clkmgr.v | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 rtl/bench/tb_clkmgr.v (limited to 'rtl') diff --git a/rtl/bench/tb_clkmgr.v b/rtl/bench/tb_clkmgr.v new file mode 100644 index 0000000..a987e1c --- /dev/null +++ b/rtl/bench/tb_clkmgr.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps + +module tb_clkmgr; + + // Input + reg fmc_clk = 1'b0; + + // Clock + always #11.111 fmc_clk = ~fmc_clk; + + // Outputs + wire io_clk; + wire sys_clk; + wire sys_rst_n; + wire core_clk; + + // Internals + reg fmc_clk_inhibit = 1'b0; + + // UUT + alpha_clkmgr uut + ( + .fmc_clk(fmc_clk & ~fmc_clk_inhibit), + .io_clk(io_clk), + .sys_clk(sys_clk), + .sys_rst_n(sys_rst_n), + .core_clk(core_clk) + ); + + // Script + initial begin + #399000; + fmc_clk_inhibit = 1'b1; + #1000; + fmc_clk_inhibit = 1'b0; + end + +endmodule -- cgit v1.2.3